Chung-Yang Huang

Publication Activity (10 Years)

Years Active: 1998-2022
Publications (10 Years): 4

Top Topics

Dynamic Characteristics

Completely Automatic

Pattern Generator

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Chin-Yi Cheng, Chien-Yi Yang, Ren-Chu Wang, Yi-Hsiang Kuo, Hao-Chung Cheng, Chung-Yang Huang
Qubit Mapping Toward Quantum Advantage. CoRR (2022)
Kuan-Lun Tseng, Yen-Liang Lin, Winston H. Hsu, Chung-Yang Huang
Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. CVPR (2017)
Kuan-Lun Tseng, Yen-Liang Lin, Winston H. Hsu, Chung-Yang Huang
Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. CoRR (2017)
Kuan Fan, Ming-Jen Yang, Chung-Yang Huang
Automatic abstraction refinement of TR for PDR. ASP-DAC (2016)
Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang
A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, Chung-Yang Huang
Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Yu-Fu Yeh, Hsin-Cheng Lin, Chung-Yang Huang
An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Shihheng Tsai, Man-Yu Li, Chung-Yang Huang
A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. ASP-DAC (2012)
Kai-Fu Tang, Po-Kai Huang, Chun-Nan Chou, Chung-Yang Huang
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. DATE (2012)
Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang, Ting-Mao Chang
SoC HW/SW verification and validation. ASP-DAC (2011)
Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. DATE (2011)
Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang
A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. ASP-DAC (2011)
Hu-Hsi Yeh, Chung-Yang Huang
Automatic constraint generation for guided random simulation. ASP-DAC (2010)
Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang
Formal deadlock checking on high-level SystemC designs. ICCAD (2010)
Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang
To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers 59 (4) (2010)
Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang
A robust functional ECO engine by SAT proof minimization and interpolation techniques. ICCAD (2010)
Shihheng Tsai, Chung-Yang Huang
A false-path aware formal static timing analyzer considering simultaneous input transitions. DAC (2009)
Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. ASP-DAC (2009)
Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang
Interpolant generation without constructing resolution graph. ICCAD (2009)
Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. DATE (2008)
Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko
Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD (2007)
Hsing-Chih Hung, Ting-Hao Lin, Chung-Yang Huang
QuteIP: An IP qualification framework for System on Chip. SoCC (2007)
Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang
QuteSAT: a robust circuit-based SAT solver for complex circuit structure. DATE (2007)
Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng
An analysis of ATPG and SAT algorithms for formal verification. HLDVT (2001)
Chung-Yang Huang, Kwang-Ting Cheng
Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (3) (2001)
Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng
Static property checking using ATPG vs. BDD techniques. ITC (2000)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49 (5) (2000)
Chung-Yang Huang, Kwang-Ting Cheng
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. DAC (2000)
Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng
LIBRA - a library-independent framework for post-layout performance optimization. ISPD (1998)