Ganapathy Parthasarathy

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 6

Top Topics

Bayesian Estimation

Top Venues

Publications

Bhuvnesh Kumar, Saurav Nanda, Ganapathy Parthasarathy, Pawan Patil, Austin Tsai, Parivesh Choudhary
HDL-GPT: High-Quality HDL is All You Need. CoRR (2024)
Bhuvnesh Kumar, Ganapathy Parthasarathy, Saurav Nanda, Sridhar Rajakumar
Optimizing Constrained Random Verification with ML and Bayesian Estimation. MLCAD (2023)
Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar
RTL Regression Test Selection using Machine Learning. ASP-DAC (2022)
Ganapathy Parthasarathy, Bhuvnesh Kumar, Saurav Nanda, Parivesh Choudhary, Sridhar Rajakumar
Optimizing ML Classification Models for Constrained EDA Resource Budgets. ICCD (2022)
Saurav Nanda, Ganapathy Parthasarathy, Parivesh Choudhary, Arun Venkatachar
Resource Aware Scheduling for EDA Regression Jobs. Euro-Par Workshops (2019)
Arun Venkatachar, S. Rajakumar, M. Chapman, Sajeewan Basuru, Ganapathy Parthasarathy, C.-C. Lin, A. Hegde, T. Li
Test Knowledge Data Base. VLSI-DAT (2017)
Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. DATE (2005)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
Structural search for RTL with predicate learning. DAC (2005)
Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
An Efficient Sequential SAT Solver With Improved Search Strategies. DATE (2005)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
RTL SAT simplification by Boolean and interval arithmetic reasoning. ICCAD (2005)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
An efficient finite-domain constraint solver for circuits. DAC (2004)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
Efficient reachability checking using sequential SAT. ASP-DAC (2004)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
Safety Property Verification Using Sequential SAT and Bounded Model Checking. IEEE Des. Test Comput. 21 (2) (2004)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
A comparison of BDDs, BMC, and sequential SAT for model checking. HLDVT (2003)
Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
SATORI - A Fast Sequential SAT Engine for Circuits. ICCAD (2003)
Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
Efficient circuit clustering for area and power reduction in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7 (4) (2002)
Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC (2002)
Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
Interconnect Resource-Aware Placement for Hierarchical FPGAs. ICCAD (2001)
Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh
Interconnect complexity-aware FPGA placement using Rent's rule. SLIP (2001)
Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng
An analysis of ATPG and SAT algorithms for formal verification. HLDVT (2001)
Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design (1999)
Ganapathy Parthasarathy, Michael L. Bushnell
Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. VTS (1998)