A comparison of BDDs, BMC, and sequential SAT for model checking.
Ganapathy ParthasarathyMadhu K. IyerKwang-Ting ChengLi-C. WangPublished in: HLDVT (2003)
Keyphrases
- model checking
- timed automata
- temporal logic
- satisfiability problem
- binary decision diagrams
- formal verification
- automated verification
- formal specification
- model checker
- finite state
- partial order reduction
- temporal properties
- verification method
- symbolic model checking
- computation tree logic
- transition systems
- finite state machines
- pspace complete
- formal methods
- concurrent systems
- bounded model checking
- reachability analysis
- epistemic logic
- linear temporal logic
- heuristic search
- asynchronous circuits
- reactive systems
- planning domains