Madhu K. Iyer

Publication Activity (10 Years)

Years Active: 1998-2005
Publications (10 Years): 0

Publications

Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. DATE (2005)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
Structural search for RTL with predicate learning. DAC (2005)
Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
An Efficient Sequential SAT Solver With Improved Search Strategies. DATE (2005)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
RTL SAT simplification by Boolean and interval arithmetic reasoning. ICCAD (2005)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
An efficient finite-domain constraint solver for circuits. DAC (2004)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
Efficient reachability checking using sequential SAT. ASP-DAC (2004)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
Safety Property Verification Using Sequential SAT and Bounded Model Checking. IEEE Des. Test Comput. 21 (2) (2004)
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
A comparison of BDDs, BMC, and sequential SAT for model checking. HLDVT (2003)
Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
SATORI - A Fast Sequential SAT Engine for Circuits. ICCAD (2003)
Madhu K. Iyer, Kwang-Ting Cheng
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. VTS (2002)
Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC (2002)
Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS (2001)
Madhu K. Iyer, Michael L. Bushnell
Effect of Noise on Analog Circuit Testing. J. Electron. Test. 15 (1-2) (1999)
Madhu K. Iyer, Michael L. Bushnell
Effect of Noise on Analog Circuit Testing. VTS (1998)