Jing-Reng Huang

Publication Activity (10 Years)

Years Active: 1999-2007
Publications (10 Years): 0

Publications

Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang
A Built-In Parametric Timing Measurement Unit. IEEE Des. Test Comput. 21 (4) (2004)
Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
An SOC Test Integration Platform and Its Industrial Realization. ITC (2004)
Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT (2002)
Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium (2002)
Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium (2002)
Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS (2001)
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
A low-cost CMOS time interval measurement core. ISCAS (4) (2001)
Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium (2001)
Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. VTS (2001)
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
A built-in timing parametric measurement unit. ITC (2001)
Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu
An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium (2000)
Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai
BRAINS: A BIST Compiler for Embedded Memories. DFT (2000)
Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang
A realistic fault model for flash memories. Asian Test Symposium (2000)
Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
A programmable built-in self-test core for embedded memories. ASP-DAC (2000)
Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16 (1) (1999)