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Test Scheduling of BISTed Memory Cores for SOC.

Chih-Wea WangJing-Reng HuangYen-Fu LinKuo-Liang ChengChih-Tsun HuangCheng-Wen WuYoun-Long Lin
Published in: Asian Test Symposium (2002)
Keyphrases
  • scheduling problem
  • memory requirements
  • computing power
  • real time
  • general purpose
  • information systems
  • resource consumption
  • batch processing
  • level parallelism
  • multicore processors
  • hardware software co design