Tsin-Yuan Chang

Publication Activity (10 Years)

Years Active: 1988-2019
Publications (10 Years): 1

Top Topics

Liquid Crystal Displays

Piecewise Linear

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE J. Solid State Circuits

Publications

Chih-Wen Lu, Pei-Yi Lai Lee, You-Gang Chang, Xing-Wei Huang, Jhih-Siou Cheng, Po-Yu Tseng, Chih-Hsien Chou, Poki Chen, Tsin-Yuan Chang, Jenny Yi-Chun Liu
A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display. IEEE J. Solid State Circuits 54 (10) (2019)
Hsi-En Liu, Shih-Che Hung, Chih-Wen Lu, Tsin-Yuan Chang
A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator. ISCAS (2014)
Yuan-Ho Chen, Jyun-Neng Chen, Tsin-Yuan Chang, Chih-Wen Lu
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Yuan-Ho Chen, Ruei-Yuan Jou, Tsin-Yuan Chang, Chih-Wen Lu
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Yuan-Ho Chen, Tsin-Yuan Chang
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2012)
Song-Nien Tang, Chi-Hsiang Liao, Tsin-Yuan Chang
An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems. IEEE J. Solid State Circuits 47 (6) (2012)
Yuan-Ho Chen, Tsin-Yuan Chang
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Yuan-Ho Chen, Chung-Yi Li, Tsin-Yuan Chang
Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (3) (2011)
Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. IEEE Trans. Very Large Scale Integr. Syst. 19 (4) (2011)
Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang
A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications. IEEE Trans. Circuits Syst. II Express Briefs (6) (2010)
Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang
Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Po-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang
IEEE Standard 1500 Compatible Delay Test Framework. IEEE Trans. Very Large Scale Integr. Syst. 17 (8) (2009)
Hung-Chih Lin, Hsiang-Han Wu, Tsin-Yuan Chang
An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement. IEEE Trans. Circuits Syst. II Express Briefs (9) (2008)
Hung-Chih Lin, Bou-Ching Fung, Tsin-Yuan Chang
A current mode adaptive on-time control scheme for fast transient DC-DC converters. ISCAS (2008)
Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. ISVLSI (2008)
Chung-Yi Li, Chia-yuan Chou, Tsin-Yuan Chang
A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range. ATS (2006)
Chung-Yi Li, Jiung-Sheng Chen, Tsin-Yuan Chang
A chaos-based pseudo random number generator using timing-based reseeding method. ISCAS (2006)
Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang
On-chip accumulated jitter measurement for phase-locked loops. ASP-DAC (2005)
Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang
A Built-In Parametric Timing Measurement Unit. IEEE Des. Test Comput. 21 (4) (2004)
Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. Asian Test Symposium (2004)
Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang
Timing measurement unit with multi-stage TVC for embedded memories. ASP-DAC (2004)
Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. ISCAS (5) (2003)
Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang
An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. Asian Test Symposium (2002)
Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang
An Access Timing Measurement Unit of Embedded Memory. Asian Test Symposium (2002)
Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. Asian Test Symposium (2001)
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
A low-cost CMOS time interval measurement core. ISCAS (4) (2001)
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
A built-in timing parametric measurement unit. ITC (2001)
Tsin-Yuan Chang, Yervant Zorian
SoC Testing and P1500 Standard. Asian Test Symposium (2000)
Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang
A realistic fault model for flash memories. Asian Test Symposium (2000)
Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16 (1) (1999)
Tsin-Yuan Chang, Jean-Bean Hsu, Cheng-Chi Wang, Yu-Shen Lin
A design for concurrent error detections in FPLAs. Great Lakes Symposium on VLSI (1992)
Chin-Long Wey, Tsin-Yuan Chang
An efficient output phase assignment for PLA minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (1) (1990)
Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. DAC (1990)
Chin-Long Wey, Tsin-Yuan Chang
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. DAC (1988)