A counterexample-guided interpolant generation algorithm for SAT-based model checking.
Cheng-Yin WuChi-An WuChien-Yu LaiChung-Yang (Ric) HuangPublished in: DAC (2013)
Keyphrases
- generation algorithm
- model checking
- bounded model checking
- formal verification
- temporal logic
- finite state
- planning domains
- model checker
- temporal properties
- computation tree logic
- formal specification
- automated verification
- partial order reduction
- linear temporal logic
- symbolic model checking
- pspace complete
- verification method
- timed automata
- epistemic logic
- concurrent systems
- process algebra
- transition systems
- formal methods
- reachability analysis
- reactive systems
- asynchronous circuits
- answer set programming
- modal logic
- web services