Synthesis and verification of cyclic combinational circuits.

Jui-Hung Chen Yung-Chih Chen Wan-Chen Weng Ching-Yi Huang Chun-Yao Wang

Published in: SoCC (2015)

Keyphrases

asynchronous circuits
logic synthesis
delay insensitive
logic circuits
analog circuits
model checking
decision trees
high speed
tunnel diode
concurrent systems
program synthesis
texture synthesis
low power
search algorithm
bayesian networks
circuit design
multi valued
verification method
image processing