Login / Signup
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays.
Chia-Cheng Wu
Kung-Han Ho
Juinn-Dar Huang
Chun-Yao Wang
Published in:
ISVLSI (2018)
Keyphrases
</>
small number
low cost
real time
image processing
general purpose
genetic algorithm
control system
probability distribution
management system
high speed
hierarchical structure