Majority logic circuits optimisation by node merging.

Chun-Che Chung Yung-Chih Chen Chun-Yao Wang Chia-Cheng Wu

Published in: ASP-DAC (2017)

Keyphrases

logic circuits
low power
functional decomposition
gate array
tunnel diode
power consumption
genetic algorithm
pattern recognition
real time
user interface
high speed
signal processing
end to end