Chung-Len Lee

Publication Activity (10 Years)

Years Active: 1990-2014
Publications (10 Years): 0

Top Topics

Buffer Management

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Chung-Yi Li, Chung-Len Lee, Ming-Hong Hu, Hwai-Pwu Chou
A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung-Len Lee
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. ASICON (2013)
Si Chen, Xiaole Cui, Chung-Len Lee
A novel test scheme for NAND flash memory based on built-in oscillator ring. ASICON (2013)
Xuan Yang, Xiaole Cui, Chao Wang, Chung-Len Lee
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. ASICON (2013)
Xiangrong Zhang, Xiaole Cui, Bo Wang, Chung-Len Lee
A UWB mixer with a balanced wide band active balun using crossing centertaped inductor. ISCAS (2013)
Yibo He, Xiaole Cui, Chung-Len Lee, Xiaoxin Cui, Yufeng Jin
New DfT architectures for 3D-SICs with a wireless test port. ASICON (2013)
Weijia Ma, Xiaole Cui, Chung-Len Lee
Enhanced error correction against multiple-bit-upset based on BCH code for SRAM. ASICON (2013)
Jin Zha, Xiaole Cui, Chung-Len Lee
Modeling and testing of interference faults in the nano NAND Flash memory. DATE (2012)
Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design. IEICE Trans. Electron. (6) (2011)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. ISCAS (2008)
Jian Ruan, Chung-Len Lee
A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. DELTA (2008)
Weibo Hu, Chung-Len Lee, Xin'an Wang
Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer. DELTA (2008)
Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. 23 (4) (2007)
Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Trans. Very Large Scale Integr. Syst. 15 (7) (2007)
Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC (2006)
Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC (2006)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Oscillation ring based interconnect test scheme for SOC. ASP-DAC (2005)
Ming Shae Wu, Chung-Len Lee
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults. IEEE Des. Test Comput. 22 (2) (2005)
Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium (2005)
Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium (2005)
Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
Multilevel full-chip routing with testability and yield enhancement. SLIP (2005)
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium (2005)
Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. Asian Test Symposium (2005)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium (2004)
Chung Liang Chen, Chung-Len Lee, Ming Shae Wu
A New Path Delay Test Scheme Based on Path Delay Inertia. Asian Test Symposium (2004)
Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen
A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium (2004)
Chin-Cheng Tsai, Chung-Len Lee
An On-Chip Jitter Measurement Circuit for the PLL. Asian Test Symposium (2003)
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19 (4) (2003)
Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE (2002)
Chih-Wen Lu, Chung-Len Lee
A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application. DELTA (2002)
Chih-Wen Lu, Chung-Len Lee
A low-power high-speed class-AB buffer amplifier for flat-panel-display application. IEEE Trans. Very Large Scale Integr. Syst. 10 (2) (2002)
Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium (2002)
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electron. Test. 18 (6) (2002)
Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electron. Test. 18 (1) (2002)
Tek Jau Tan, Chung-Len Lee
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. VTS (2001)
Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee
A computer aided engineering system for memory BIST. ASP-DAC (2001)
Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. 17 (6) (2001)
Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir
Oscillation Ring Delay Test for High Performance Microprocessors. J. Electron. Test. 16 (1-2) (2000)
Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Fault diagnosis for linear analog circuits. Asian Test Symposium (2000)
Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE (2000)
Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium (2000)
Hsing-Chung Liang, Chung-Len Lee
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. J. Inf. Sci. Eng. 16 (5) (2000)
Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su
A methodology for fault model development for hierarchical linear systems. Asian Test Symposium (2000)
Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16 (5) (2000)
Hsing-Chung Liang, Chung-Len Lee
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. Asian Test Symposium (1999)
Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. 15 (6) (1999)
Chauchin Su, Yue-Tsang Chen, Chung-Len Lee
Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium (1999)
Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. 14 (3) (1998)
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS (1998)
Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
Maximization of power dissipation under random excitation for burn-in testing. ITC (1998)
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
Identifying invalid states for sequential circuit test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (9) (1997)
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
Functional test pattern generation for CMOS operational amplifier. VTS (1997)
Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen
Fault diagnosis of odd-even sorting networks. Asian Test Symposium (1997)
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium (1996)
Chung-Len Lee, Meng-Lieh Sheu
A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines. IEEE Trans. Computers 45 (9) (1996)
Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang
On Designing of 4-Valued Memory with Double-Gate TFT. ISMVL (1995)
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
Identifying Untestable Faults in Sequential Circuits. IEEE Des. Test Comput. 12 (3) (1995)
Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri
Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium (1995)
Meng-Lieh Sheu, Chung-Len Lee
A programmable multiple-sequence generator for BIST applications. Asian Test Symposium (1995)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen
Fanout fault analysis for digital logic circuits. Asian Test Symposium (1995)
Hui Min Wang, Chung-Len Lee, Jwu E. Chen
Factorization of Multi-Valued Logic Functions. ISMVL (1995)
Beyin Chen, Chung-Len Lee
Universal test set generation for CMOS circuits. J. Electron. Test. 6 (3) (1995)
Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
Identification of robust untestable path delay faults. Asian Test Symposium (1995)
Meng-Lieh Sheu, Chung-Len Lee
Simplifying Sequential Circuit Test Generation. IEEE Des. Test Comput. 11 (3) (1994)
Yeong-Jar Chang, Chung-Len Lee
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic. ISMVL (1994)
Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC (1994)
Hui Min Wang, Chung-Len Lee, Jwu E. Chen
Complete Test Set for Multiple-Valued Logic Networks. ISMVL (1994)
Hui Min Wang, Chung-Len Lee, Jwu E. Chen
Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL (1994)
Beyin Chen, Chung-Len Lee
A complement-based fast algorithm to generate universal test sets for multi-output functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (3) (1994)
Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee
TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC (1994)
Chung-Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang
MT-SIM a mixed-level transition fault simulator based on parallel patterns. J. Electron. Test. 3 (1) (1992)
Ching Ping Wu, Chung-Len Lee, Wen-Zen Shen
SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence. EURO-DAC (1992)
Hui Min Wang, Chung-Len Lee, Jwu E. Chen
Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL (1992)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (12) (1991)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
Checkpoints in irredundant two-level combinational circuits. J. Electron. Test. 2 (4) (1991)
Wen Ching Wu, Chung-Len Lee
A Probabilistic Testability Measure for Delay Faults. DAC (1991)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
Single-fault fault collapsing analysis in sequential logic circuits. ITC (1990)
Tyh-Song Hwang, Chung-Len Lee, Wen-Zen Shen, Ching Ping Wu
A Parallel Pattern Mixed-Level Fault Simulator. DAC (1990)