Chauchin Su

Publication Activity (10 Years)

Years Active: 1993-2019
Publications (10 Years): 3

Top Topics

Infrared Sensors

High Temperature

Digital Signal Processing

Top Venues

IEEE J. Solid State Circuits

Publications

Ting-You Lin, Chauchin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao-Chang Huang
Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation. DATE (2019)
Ting-You Lin, Yingchieh Ho, Chauchin Su
LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs. Sensors 17 (6) (2017)
Yuhwai Tseng, Ting-You Lin, Songwen Yau, Yingchieh Ho, Chauchin Su
A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system. ISOCC (2016)
Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. IEEE J. Solid State Circuits 49 (4) (2014)
Yingchieh Ho, Chou-Ming Kuo, Chauchin Su
A low-power analog-to-digital converter with digitalized amplifier for PAM systems. MWSCAS (2014)
Yingchieh Ho, Yu-Sheng Yang, Chiachi Chang, Chauchin Su
A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO. IEEE J. Solid State Circuits 48 (11) (2013)
Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. VLSIC (2012)
Yuhwai Tseng, Yingchieh Ho, Shuoting Kao, Chauchin Su
A 0.09 µW Low Power Front-End Biopotential Amplifier for Biosignal Recording. IEEE Trans. Biomed. Circuits Syst. 6 (5) (2012)
Hungkai Chen, Yingchieh Ho, Chauchin Su
Cumulative Differential Nonlinearity Testing of ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2012)
Yingchieh Ho, Chauchin Su
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters. IEEE J. Solid State Circuits 47 (5) (2012)
Yingchieh Ho, Chiachi Chang, Chauchin Su
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs (1) (2012)
Yingchieh Ho, Hungkai Chen, Chauchin Su
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2) (2012)
Yingchieh Ho, Yu-Sheng Yang, Chauchin Su
A 0.2-0.6 V ring oscillator design using bootstrap technique. A-SSCC (2011)
Hung-Wen Lin, Yingchieh Ho, YingLin Fa, Chauchin Su
A 5Gb/s pulse signaling interface for low power on-chip data communication. ISCAS (2010)
Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. IEICE Trans. Inf. Syst. (6) (2010)
Jen-Chien Hsu, Chauchin Su
Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks. IEEE Trans. Instrum. Meas. 59 (4) (2010)
Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2010)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu
Design of an All-Digital LVDS Driver. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2009)
Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu
A Tree-Topology Multiplexer for Multiphase Clock System. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2009)
Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. IEICE Trans. Commun. (11) (2009)
Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu
A Scalable Digitalized Buffer for Gigabit I/O. IEEE Trans. Circuits Syst. II Express Briefs (10) (2008)
Hungwen Lu, Chauchin Su, Chien-Nan Liu
A scalable digitalized buffer for gigabit I/O. CICC (2008)
Jen-Chien Hsu, Chauchin Su
BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops. IEEE Trans. Instrum. Meas. 57 (2) (2008)
Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, Chauchin Su
Filter Approach. IEEE Trans. Circuits Syst. Video Technol. 18 (12) (2008)
Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. 23 (4) (2007)
Hung-Kai Chen, Chauchin Su
A Test and Diagnosis Methodology for RF Transceivers. ATS (2007)
Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su
Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Trans. Electron. (11) (2006)
Chih-Hu Wang, Bore-Kuen Lee, Wei-Hang Tseng, Chung-Hsi Fu, Chauchin Su, Chien-Nan Jimmy Liu
Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. SMC (2006)
Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Maohsuan Chou, Jen-Chien Hsu, Chauchin Su
A Digital BIST Methodology for Spread Spectrum Clock Generators. ATS (2006)
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC (2006)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Oscillation ring based interconnect test scheme for SOC. ASP-DAC (2005)
Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su
A spread spectrum clock generator for SATA-II. ISCAS (3) (2005)
Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
Multilevel full-chip routing with testability and yield enhancement. SLIP (2005)
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium (2005)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium (2004)
Chauchin Su, Wei-Juo Wang, Chih-Hu Wang, I. S. Tseng
A novel LCD driver testing technique using logic test channels. ASP-DAC (2003)
Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng
1149.4 Based On-Line Quiescent State Monitoring Technique. VTS (2003)
Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electron. Test. 18 (1) (2002)
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
Intrinsic response for analog module testing using an analog testability bus. ACM Trans. Design Autom. Electr. Syst. 6 (2) (2001)
Yue-Tsang Chen, Chauchin Su
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. VTS (2001)
Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee
A computer aided engineering system for memory BIST. ASP-DAC (2001)
Chauchin Su, Wenliang Tseng
Configuration free SoC interconnect BIST methodology. ITC (2001)
Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. 17 (6) (2001)
Chauchin Su, Yue-Tsang Chen, Shenshung Chiang
Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. J. Inf. Sci. Eng. 16 (5) (2000)
Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Fault diagnosis for linear analog circuits. Asian Test Symposium (2000)
Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE (2000)
Chauchin Su, Yue-Tsang Chen
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. VTS (2000)
Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium (2000)
Chauchin Su, Yue-Tsang Chen
Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (4) (2000)
Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su
A methodology for fault model development for hierarchical linear systems. Asian Test Symposium (2000)
Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16 (5) (2000)
Chauchin Su, Shyh-Jye Jou
Decentralized BIST Methodology for System Level Interconnects. J. Electron. Test. 15 (3) (1999)
Chauchin Su, Yue-Tsang Chen, Chung-Len Lee
Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium (1999)
Chauchin Su, Yue-Tsung Chen
Comprehensive Interconnect BIST Methodology for Virtual Socket Interface. Asian Test Symposium (1998)
Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen
Boundary scan BIST methodology for reconfigurable systems. ITC (1998)
Chauchin Su
A linear optimal test generation algorithm for interconnect testing. ICCAD (1998)
Yue-Tsang Chen, Chauchin Su
Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. Asian Test Symposium (1998)
Chauchin Su, E. Y. Chen, Shyh-Jye Jou
Structural approach for performance driven ECC circuit synthesis. ASP-DAC (1997)
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. ITC (1997)
Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen
Analog signal metrology for mixed signal ICs. Asian Test Symposium (1997)
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting
Metrology for analog module testing using analog testability bus. ICCAD (1996)
Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting
Syndrome Simulation And Syndrome Test For Unscanned Interconnects. Asian Test Symposium (1996)
Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting
Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. ED&TC (1996)
Chauchin Su, Shenshung Chiang, Shyh-Jye Jou
Impulse response fault model and fault extraction for functional level analog circuit diagnosis. ICCAD (1995)
Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su
Circuits Design Optimization Using Symbolic Approach. ISCAS (1995)
Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su
A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. ISCAS (1995)
Chauchin Su
Random Testing of Interconnects in A Boundary Scan Environment. EDAC-ETC-EUROASIC (1994)
Chauchin Su, Kychin Hwang, Shyh-Jye Jou
Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. ITC (1994)
Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang
Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. ISCAS (1994)
Chauchin Su, Jyrghong Wang
ECCSyn: a Synthesis Tool for ECC Circuits. ISCAS (1993)
Chiyuan Chang, Chauchin Su
A Universal BIST Methodology for Interconnects. ISCAS (1993)
Chauchin Su, Kychin Hwang
A Serial-Scan Test-Vector-Compression Methodology. ITC (1993)