Multilevel Full-Chip Routing With Testability and Yield Enhancement.
Katherine Shu-Min LiYao-Wen ChangChung-Len LeeChauchin SuJwu E. ChenPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
- high speed
- low cost
- image enhancement
- routing algorithm
- image processing
- ad hoc networks
- vlsi design
- network topology
- vlsi implementation
- routing protocol
- routing problem
- physical design
- inter domain
- programmable logic
- single chip
- high density
- analog vlsi
- functional verification
- contrast enhancement
- low power
- evolutionary algorithm