Katherine Shu-Min Li

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 48

Top Topics

Pattern Recognition

Top Venues

Publications

Katherine Shu-Min Li, Fang-Chi Wu, Jian-De Li, Sying-Jyan Wang
Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Tzung-Pei Hong, Meng-Jui Kuo, Chun-Hao Chen, Katherine Shu-Min Li
Federated Erasable-Itemset Mining with Quasi-Erasable Itemsets. ACIIDS (1) (2024)
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults. Integr. 89 (2023)
Nadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho
Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing. ITC (2023)
Nadun Sinhabahu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho
Trojan Insertions of Fully Programmable Valve Arrays. ETS (2022)
Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai
Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. ITC (2022)
Nadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang
Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test. ITC (2022)
Sying-Jyan Wang, Yen-Chang Shih, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong
Improving IJTAG Test Efficiency and Security. VLSI-DAT (2022)
Yi-Hsuan Chuang, Ja-Hwung Su, Ding-Hong Han, Yi-Wen Liao, Yeong-Chyi Lee, Yu-Fan Cheng, Tzung-Pei Hong, Katherine Shu-Min Li, Hsin-You Ou, Yi Lu, Chih-Chi Wang
Effective Natural Language Processing and Interpretable Machine Learning for Structuring CT Liver-Tumor Reports. IEEE Access 10 (2022)
Sying-Jyan Wang, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong
Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication. ATS (2022)
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults. ASP-DAC (2022)
Sying-Jyan Wang, Tzu-Heng Chang, Katherine Shu-Min Li
Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs. VLSI-DAT (2021)
Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS (2021)
Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho
Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. DATE (2021)
Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC (2021)
Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. ITC (2021)
Katherine Shu-Min Li, Leon Li-Yang Chen, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng
Integrated Scratch Marker for Wafer Defect Diagnosis. ITC-Asia (2021)
Sying-Jyan Wang, Yu-Sheng Chen, Katherine Shu-Min Li
Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (2) (2021)
Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang
Innovative Practice on Wafer Test Innovations. VTS (2020)
Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee
TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. ITC (2020)
Tzung-Pei Hong, Cheng-Yu Lin, Wei-Ming Huang, Katherine Shu-Min Li, Shyue-Liang Leon Wang, Jerry Chun-Wei Lin
Using Tree Structure to Mine High Temporal Fuzzy Utility Itemsets. IEEE Access 8 (2020)
Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, Gus Chang-Hung Han
PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques. ETS (2020)
Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. DATE (2020)
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
Watermarking for Paper-Based Digital Microfluidic Biochips. ITC-Asia (2020)
Sying-Jyan Wang, Cheng Xuan Cai, Yen-Wen Tseng, Katherine Shu-Min Li
Feature Selection for Malicious Traffic Detection with Machine Learning. ICS (2020)
Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee
TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning. ITC (2019)
Sying-Jyan Wang, Kuan-Ting Yeh, Katherine Shu-Min Li
Exploiting distribution of unknown values in test responses to optimize test output compactors. Integr. 65 (2019)
Jian-De Li, Chun-Hao Kuo, Guan-Ruei Lu, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho, Hung-Ming Chen, Shiyan Hu
Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. Microelectron. J. 83 (2019)
Sying-Jyan Wang, Yu-Shen Chen, Katherine Shu-Min Li
Adversarial Attack against Modeling Attack on PUFs. DAC (2019)
Jia-Lin Wu, Katherine Shu-Min Li, Jain-De Li, Sying-Jyan Wang, Tsung-Yi Ho
SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips. VLSI-DAT (2018)
Sying-Jyan Wang, Chin-Hung Lien, Katherine Shu-Min Li
Register PUF with No Power-Up Restrictions. ISCAS (2018)
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
Digital Rights Management for Paper-Based Microfluidic Biochips. ATS (2018)
Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
Design-for-testability for paper-based digital microfluidic biochips. DFT (2017)
Katherine Shu-Min Li, Sying-Jyan Wang
Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip. ACM Trans. Design Autom. Electr. Syst. 22 (4) (2017)
Edwin C. Jones, Kathleen E. Wage, Sanjit A. Seshia, Susan M. Lord, Michael E. Auer, Lance C. Pérez, Katherine Shu-Min Li, S. L. Krishna Priya, Sasha Nikolic, Francisco Arcega, Richard A. Layton, Matthew W. Ohland, Kayode Peter Ayodele, Isaac A. Inyang, Lawrence O. Kehinde, Jana Reisslein, Amy M. Johnson, Martin Reisslein, James L. Huff, Joachim Walther, Brent K. Jesiek, Carla B. Zoltowski, William C. Oakes, Natasha Nesiba, Enrico Pontelli, Timothy Staley, Melany M. Ciampi, John Heywood, Diane T. Rover, Raman M. Unnikrishnan, Agnieszka Miguel
2016 IEEE Education Society Awards, 2016 Frontiers in Education Conference Awards, and Selected IEEE Awards. IEEE Trans. Educ. 60 (1) (2017)
Katherine Shu-Min Li, Sying-Jyan Wang, Ruei-Ting Gu, Bo-Chuan Cheng
Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. IEEE Des. Test 34 (6) (2017)
Sying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li
Testing Clock Distribution Networks. ATS (2017)
Sying-Jyan Wang, Jhih-Yu Wei, Shih-Heng Huang, Katherine Shu-Min Li
Test generation for combinational hardware Trojans. AsianHOST (2016)
Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips. ASP-DAC (2016)
Liang-Bi Chen, Wan-Jung Chang, Jian-Ping Su, Ji-Yi Ciou, Yi-Jhan Ciou, Cheng-Chin Kuo, Katherine Shu-Min Li
A wearable-glasses-based drowsiness-fatigue-detection system for improving road safety. GCCE (2016)
Hong-Yuan Li, Liang-Bi Chen, Wan-Jung Chang, Jing-Jou Tang, Katherine Shu-Min Li
Design and development of an extensible multi-protocol automotive gateway. ICCE-TW (2016)
Liang-Bi Chen, Hong-Yuan Li, Wan-Jung Chang, Jing-Jou Tang, Katherine Shu-Min Li
WristEye: Wrist-Wearable Devices and a System for Supporting Elderly Computer Learners. IEEE Access 4 (2016)
Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
Test and diagnosis of paper-based microfluidic biochips. VTS (2016)
Liang-Bi Chen, Bo-Chuan Cheng, You-Chiun Wang, Katherine Shu-Min Li, Jing-Jou Tang
An efficient fault tolerance path finding algorithm for improving the robustness of multichannel wireless mesh networks. ICCE (2016)
Liang-Bi Chen, Wan-Jung Chang, Kuen-Min Lee, Chi-Wei Huang, Katherine Shu-Min Li
A Comprehensive Medicine Management System with Multiple Sources in a Nursing Home in Taiwan. IEICE Trans. Inf. Syst. (6) (2016)
Liang-Bi Chen, Chia-Wei Tsai, Wan-Jung Chang, Yuh-Ming Cheng, Katherine Shu-Min Li
A real-time mobile emergency assistance system for helping deaf-mute people/elderly singletons. ICCE (2016)
Liang-Bi Chen, Meng-Kang Chiang, Chia-Lin Liu, Katherine Shu-Min Li, Jing-Jou Tang
An adaptive residential energy management scheme in the smart home. ICCE (2016)
Sying-Jyan Wang, Ting-Jui Choi, Katherine Shu-Min Li
Side-Channel Attack on Flipped Scan Chains. ATS (2016)
Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. DATE (2015)
Liang-Bi Chen, Hong-Yuan Li, Wan-Jung Chang, Jing-Jou Tang, Katherine Shu-Min Li
An intelligent vehicular telematics platform for vehicle driving safety supporting system. ICCVE (2015)
Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng
Optimized Pre-bond Test Methodology for Silicon Interposer Testing. ATS (2014)
Sying-Jyan Wang, Tsung-Huei Tzeng, Katherine Shu-Min Li
Fast and accurate statistical static timing analysis. ISCAS (2014)
Katherine Shu-Min Li, Yingchieh Ho, Yu-Wei Yang, Liang-Bi Chen
An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip. IEICE Trans. Inf. Syst. (9) (2014)
Sying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li
Improving Output Compaction Efficiency with High Observability Scan Chains. ATS (2014)
Chung Heng Chuang, Tsung-Hsing Lin, Liang-Bi Chen, Tung-Lin Lee, Chaio Hsuan Chuang, Katherine Shu-Min Li, Chih-Lin Hung, Chao-Wen Wu
A Hybrid Multi-functions Digital Public Address System with Earthquake Early Warning. IIH-MSP (2014)
Katherine Shu-Min Li
CusNoC: Fast Full-Chip Custom NoC Generation. IEEE Trans. Very Large Scale Integr. Syst. 21 (4) (2013)
Katherine Shu-Min Li, Yingchieh Ho, Liang-Bi Chen
Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process. VLSI-DAT (2013)
Sying-Jyan Wang, Yu-Siao Chen, Katherine Shu-Min Li
Low-cost testing of TSVs in 3D stacks with pre-bond testable dies. VLSI-DAT (2013)
Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu
A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. Asian Test Symposium (2013)
Katherine Shu-Min Li, Yi-Yu Liao
IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Sying-Jyan Wang, Cheng-Hao Lin, Katherine Shu-Min Li
Synthesis of 3D clock tree with pre-bond testability. ISCAS (2013)
Katherine Shu-Min Li
Oscillation and Transition Tests for Synchronous Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator. Asian Test Symposium (2013)
Bo-Chuan Cheng, Katherine Shu-Min Li, Sying-Jyan Wang
De Bruijn graph-based communication modeling for fault tolerance in smart grids. APCCAS (2012)
Katherine Shu-Min Li, Yi-Yu Liao
Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Sying-Jyan Wang, Han-Hsuan Hsu, Katherine Shu-Min Li
Low-power delay test architecture for pre-bond test. ISCAS (2012)
Meng-Kang Chiang, Katherine Shu-Min Li
Intelligent home management in the smart grids. APCCAS (2012)
Yi-Xue Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li
Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits. SoCC (2011)
Katherine Shu-Min Li, Chih-Yun Pai, Liang-Bi Chen
Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Chih-Yun Pai, Ruei-Ting Gu, Bo-Chuan Cheng, Liang-Bi Chen, Katherine Shu-Min Li
A Unified Interconnects Testing Scheme for 3D Integrated Circuits. Asian Test Symposium (2011)
Katherine Shu-Min Li, Jr-Yang Huang
Synthesizing Multiple Scan Trees to Optimize Test Application Time. IEEE Des. Test Comput. 28 (2) (2011)
Katherine Shu-Min Li
Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (4) (2010)
Chih-Yun Pai, Katherine Shu-Min Li
Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure. Asian Test Symposium (2010)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang
IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency. Asian Test Symposium (2009)
Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang
Level Converting Scan Flip-flops. ISCAS (2009)
Katherine Shu-Min Li, Yu-Chen Hung, Jr-Yang Huang
Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint. Asian Test Symposium (2009)
Yu-Wei Yang, Katherine Shu-Min Li
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement. ASP-DAC (2009)
Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li
Low Peak Power ATPG for n-Detection Test. ISCAS (2009)
Sying-Jyan Wang, Katherine Shu-Min Li, Shih-Cheng Chen, Huai-Yan Shiu, Yun-Lung Chu
Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li
Layout-aware scan chain reorder for launch-off-shift transition test coverage. ACM Trans. Design Autom. Electr. Syst. 13 (4) (2008)
Katherine Shu-Min Li, Jr-Yang Huang
Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization. ATS (2008)
Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li
Design and analysis of skewed-distribution scan chain partition for improved test data compression. ISCAS (2008)
Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture. ATS (2007)
Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. 23 (4) (2007)
Sying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis. ATS (2007)
Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li
Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. ISCAS (2007)
Sying-Jyan Wang, Kuo-Lin Peng, Katherine Shu-Min Li
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage. ATS (2006)
Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC (2006)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
Oscillation ring based interconnect test scheme for SOC. ASP-DAC (2005)
Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
Multilevel full-chip routing with testability and yield enhancement. SLIP (2005)
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium (2005)
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium (2004)
Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang
Noise-aware buffer planning for interconnect-driven floorplanning. ASP-DAC (2003)