Chun-Lung Hsu

Publication Activity (10 Years)

Years Active: 2003-2021
Publications (10 Years): 18

Top Topics

Neurological Disorders

Foreseeable Future

Head Orientation

Top Venues

J. Electron. Test.

IEEE Trans. Very Large Scale Integr. Syst.

Asian Test Symposium

Publications

Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS (2021)
Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase, Chun-Lung Hsu, Chi-Tien Sun
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory. J. Electron. Test. 37 (4) (2021)
Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC (2021)
Tommy Sugiarto, Chun-Lung Hsu, Chi-Tien Sun, Wei-Chun Hsu, Shu-Hao Ye, Kuan-Ting Lu
Surface EMG vs. High-Density EMG: Tradeoff Between Performance and Usability for Head Orientation Prediction in VR Application. IEEE Access 9 (2021)
Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun
ECC Caching Techniques for Protecting NAND Flash Memories. ITC-Asia (2020)
Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun
Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory. VLSI-DAT (2020)
Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi
Fault-Aware Dependability Enhancement Techniques for Flash Memories. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Shi-Rou Lin, Wei-Hung Lin, Shih-Hsu Huang, Chun-Lung Hsu, Chi-Tien Sun
Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design. ICCE-TW (2020)
Tommy Sugiarto, Chun-Lung Hsu, Chi-Tien Sun, Shu-Hao Ye, Kuan-Ting Lu, Wei-Chun Hsu
Head-Orientation-Prediction Based on Deep Learning on sEMG for Low-Latency Virtual Reality Application. IRC (2020)
Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun
Testing of Configurable 8T SRAMs for In-Memory Computing. ATS (2020)
Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 3DIC (2019)
Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
Testing of In-Memory-Computing 8T SRAMs. DFT (2019)
Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
Testing stuck-open faults of priority address encoder in content addressable memories. ASP-DAC (2019)
Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. J. Electron. Test. 35 (4) (2019)
Yu-Ting Li, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
Diagnosis of Resistive Nonvolatile-8T SRAMs. ISOCC (2018)
Wei-Chun Hsu, Tommy Sugiarto, Yi-Jia Lin, Fu-Chi Yang, Zheng-Yi Lin, Chi-Tien Sun, Chun-Lung Hsu, Kuan-Nien Chou
Multiple-Wearable-Sensor-Based Gait Classification and Analysis in Patients with Neurological Disorders. Sensors 18 (10) (2018)
Kun-Lun Luo, Ming-Hsueh Wu, Chun-Lung Hsu, Chen-An Chen
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. J. Electron. Test. 32 (2) (2016)
Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. ASP-DAC (2015)
Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. Asian Test Symposium (2013)
Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai, Liang-Chia Cheng
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. Asian Test Symposium (2013)
Chun-Lung Hsu, Yu-Sheng Huang, Fong-Chao Lee
Interlaced switch boxes placement for three-dimensional FPGA architecture design. Int. J. Circuit Theory Appl. 40 (5) (2012)
Chang-Hsin Cheng, Yu Liu, Chun-Lung Hsu
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Chang-Hsin Cheng, Chun-Lung Hsu, Chung-Kai Liu, Shih-Yin Lin
High reliability built-in self-detection and self-correction design for DCT/IDCT application. SoCC (2011)
Chun-Lung Hsu, Yu-Sheng Huang, Ming-Da Chang, Hung-Yen Huang
Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder. IEEE Trans. Computers 60 (5) (2011)
Chun-Lung Hsu, Chen-Wei Lan, Yu-Chih Lo, Yu-Sheng Huang
Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications. DFT (2010)
Min-Ju Chan, Chun-Lung Hsu
A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip. DFT (2010)
Chun-Lung Hsu, Ching-Fen Wu
High-performance 3D-SRAM architecture design. APCCAS (2010)
Chun-Lung Hsu, Chang-Hsin Cheng, Yu Liu
Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Hung-Yen Huang, Yu-Sheng Huang, Chun-Lung Hsu
Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits. APCCAS (2010)
Chun-Lung Hsu, Ting-Hsuan Chen
Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA. IEEE Trans. Instrum. Meas. 58 (7) (2009)
Chun-Lung Hsu, Yi-Ting Lai
Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application. IEEE Trans. Instrum. Meas. 58 (6) (2009)
Chun-Lung Hsu, Mean-Hom Ho, Chin-Feng Lin
Testing Scheme for CMOS Integrated Circuits. IEEE Trans. Instrum. Meas. 58 (7) (2009)
Yu-Sheng Huang, Chen-Kai Chen, Chun-Lung Hsu
Efficient built-in self-test for video coding cores: A case study on motion estimation computing array. APCCAS (2008)
Chun-Lung Hsu, Yu-Sheng Huang
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. J. Signal Process. Syst. 52 (3) (2008)
Chun-Lung Hsu, Mean-Hom Ho
High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Chun-Lung Hsu, Mean-Hom Ho, Chin-Feng Lin
New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2006)
Chun-Lung Hsu, Mean-Hom Ho, Yu-Kuan Wu, Ting-Hsuan Chen
Design of Low-Frequency Low-Pass Filters for Biomedical Applications. APCCAS (2006)
Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen
An Adaptive Low-Power Control Scheme for On-Chip Network Applications. APCCAS (2006)
Chun-Lung Hsu, Yu-Kuan Wu, Yi-Ting Lai, Mean-Horn Ho
Design of current-mode resonator for wireless applications. ISCAS (2006)
Chun-Lung Hsu, Wen-Tso Wang, Ying-Fu Hong
Frequency-Scaling Approach for Managing Power Consumption in NOCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Chun-Lung Hsu, Yi-Ting Lai, Shu-Wei Wang
Built-in self-test for phase-locked loops. IEEE Trans. Instrum. Meas. 54 (3) (2005)
Chun-Lung Hsu
Control and Observation Structure for Analog Circuits with Current Test Data. J. Electron. Test. 20 (1) (2004)
Chun-Lung Hsu, Wu-Hung Lu
Design of High-Performance Charge-Pump Circuit for PLL Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)