An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST.

Liang-Che Li Wen-Hsuan Hsu Kuen-Jong Lee Chun-Lung Hsu

Published in: ASP-DAC (2015)

Keyphrases

probabilistic model
main contribution
test cases
database
high speed
test data
built in self test
test data generation
integrated circuit
statistical tests
low cost
associative memory
wireless sensor networks
genetic algorithm
test suite
test generation
test sequences
neural network
model based testing
data sets