Kuen-Jong Lee

ORCID

Publication Activity (10 Years)

Years Active: 1990-2022
Publications (10 Years): 41

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ITC

ATS

ITC-Asia

Publications

Zhi-Wei Lai, Po-Hua Huang, Kuen-Jong Lee
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function. J. Electron. Test. 38 (5) (2022)
Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Shih-Chun Yeh, Kuen-Jong Lee, Dong-Yi Chen
An Authentication-Based Secure IJTAG Network. ATS (2022)
Kuen-Jong Lee, Ching-An Liu, Chia-Chi Wu
A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing. IEEE Trans. Emerg. Top. Comput. 10 (1) (2022)
Kuen-Jong Lee, Zheng-Yao Lu, Shih-Chun Yeh
A Secure JTAG Wrapper for SoC Testing and Debugging. IEEE Access 10 (2022)
Yan-Fu Chen, Duo-Yao Kang, Kuen-Jong Lee
Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks. ITC (2022)
Kuen-Jong Lee, Cheng-Hung Wu, Tsung-Yu Hou
An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS (2022)
Duo-Yao Kang, Shiou-Ning Lin, Kuen-Jong Lee
Diagnosing Transition Delay Faults under Scan-Based Logic Array. ITC-Asia (2022)
Hung-Yao Chi, Kuen-Jong Lee, Tzu-Chun Jao
Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors. ATS (2021)
Yu-Hsiang Chen, Chia-Ming Hsu, Kuen-Jong Lee
Test Chips With Scan-Based Logic Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS (2020)
Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (6) (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC (2020)
Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Chao-Jun Shang, Cheng-Hung Wu, Kuen-Jong Lee, Yu-Hsiang Chen
A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model. VLSI-DAT (2019)
Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. ITC (2019)
Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (2) (2019)
Man-Hsuan Kuo, Chun-Ming Hu, Kuen-Jong Lee
Time-Related Hardware Trojan Attacks on Processor Cores. ITC-Asia (2019)
Zhi-Wei Lai, Kuen-Jong Lee
Using Unstable SRAM Bits for Physical Unclonable Function Applications on Off-The-Shelf SRAM. APCCAS (2019)
Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
Deep Learning Based Test Compression Analyzer. ATS (2019)
Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. ITC (2018)
Chia-Chi Wu, Man-Hsuan Kuo, Kuen-Jong Lee
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks. ATS (2018)
Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy
A Repair-for-Diagnosis Methodology for Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Chun-Wei Wu, Kuen-Jong Lee, Alan P. Su
A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip. IEEE Trans. Computers 67 (9) (2018)
Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. ITC-Asia (2018)
Wen-Hsuan Hsu, Michael Andreas Kochte, Kuen-Jong Lee
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (6) (2017)
Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy
Test generation for open and delay faults in CMOS circuits. ITC-Asia (2017)
Shuo-Lian Hong, Kuen-Jong Lee
A run-pause-resume silicon debug technique for multiple clock domain systems. ITC-Asia (2017)
Jhen-Zong Chen, Kuen-Jong Lee
Test Stimulus Compression Based on Broadcast Scan With One Single Input. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (1) (2017)
Chang-Wen Chen, Yi-Cheng Kong, Kuen-Jong Lee
Test Compression with Single-Input Data Spreader and Multiple Test Sessions. ATS (2017)
Shuo-Lian Hong, Kuen-Jong Lee
A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. ITC (2017)
Hsin-Pang Kuo, Alan P. Su, Kuen-Jong Lee
A low power synthesis flow for multi-rate systems. VLSI-DAT (2017)
Wei-Cheng Lien, Kuen-Jong Lee
Output bit selection methodology for test response compaction. ITC (2016)
Cheng-Hung Wu, Kuen-Jong Lee
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement. ITC (2016)
Sheng-Lin Lin, Cheng-Hung Wu, Kuen-Jong Lee
Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis. ATS (2016)
Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee
Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults. ASP-DAC (2016)
Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. ASP-DAC (2016)
Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte
An on-chip self-test architecture with test patterns recorded in scan chains. ITC (2016)
Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich
Autonomous Testing for 3D-ICs with IEEE Std. 1687. ATS (2016)
Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. DATE (2015)
Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. ASP-DAC (2015)
Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee
Improve transition fault diagnosability via observation point insertion. VLSI-DAT (2015)
Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee
Distinguishing dynamic bridging faults and transition delay faults. ASICON (2015)
Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh
Output-bit selection with X-avoidance using multiple counters for test-response compaction. ETS (2014)
Kuen-Jong Lee, Cheng-Hung Wu
An efficient diagnosis-aware pattern generation procedure for transition faults. ITC (2014)
Cheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien
An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model. VTS (2014)
Chin-Yao Chang, Kuen-Jong Lee
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty
Efficient LFSR Reseeding Based on Internal-Response Feedback. J. Electron. Test. 30 (6) (2014)
Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh
Output selection for test response compaction based on multiple counters. VLSI-DAT (2014)
Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Cheng-Hung Wu, Kuen-Jong Lee
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults. ATS (2014)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty
A New LFSR Reseeding Scheme via Internal Response Feedback. Asian Test Symposium (2013)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu
Counter-Based Output Selection for Test Response Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (1) (2013)
Kuen-Jong Lee, Chin-Yao Chang, Hung-Yang Yang
An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip. VLSI-DAT (2013)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Wee-Lung Ang
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Wei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee
Routing-efficient implementation of an internal-response-based BIST architecture. VLSI-DAT (2012)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. Asian Test Symposium (2012)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Shih-Shiun Chien, Krishnendu Chakrabarty
Accumulator-based output selection for test response compaction. ISCAS (2012)
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (5) (2012)
Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, Kuen-Jong Lee, Chin-Long Wey
Programmable System-on-Chip for Silicon Prototyping. IEEE Trans. Ind. Electron. 58 (3) (2011)
Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh
Test Response Compaction via Output Bit Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (10) (2011)
Kuen-Jong Lee, Alan P. Su, Long-Feng Chen, Jia-Wei Jhou, Jiff Kuo, Mark Liu
A software/hardware co-debug platform for multi-core systems. ASICON (2011)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (6) (2011)
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Kuen-Jong Lee, Chin-Yao Chang, I-Jou Chen
EPIDETOX: an ESL platform for integrated circuit design and tool exploration. CODES+ISSS (2011)
Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. IEEE Trans. Very Large Scale Integr. Syst. 18 (7) (2010)
Wei-Cheng Lien, Kuen-Jong Lee
A Complete Logic BIST Technology with No Storage Requirement. Asian Test Symposium (2010)
Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su
Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. Asian Test Symposium (2009)
Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee
Tolerance of performance degrading faults for effective yield improvement. ITC (2009)
Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao
Full System Simulation and Verification Framework. IAS (2009)
Kuen-Jong Lee, Si-Yuan Liang, Alan P. Su
A low-cost SOC debug platform based on on-chip test architectures. SoCC (2009)
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Des. Test Comput. 26 (1) (2009)
Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen
A Software-Based Test Methodology for Direct-Mapped Data Cache. ATS (2008)
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC (2008)
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
A hybrid software-based self-testing methodology for embedded processor. SAC (2008)
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
A hybrid self-testing methodology of processor cores. ISCAS (2008)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Trans. Reliab. 57 (1) (2008)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE (2007)
Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You
Test Efficiency Analysis and Improvement of SOC Test Platforms. ATS (2007)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS (2006)
Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. SoCC (2006)
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
A novel test methodology based on error-rate to support error-tolerance. ITC (2005)
Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee
A high speed BIST architecture for DDR-SDRAM testing. MTDT (2005)
Wei-Lun Wang, Kuen-Jong Lee
A complete memory address generator for scan based March algorithms. MTDT (2005)
Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong
An embedded processor based SOC test platform. ISCAS (3) (2005)
Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang
A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. Asian Test Symposium (2004)
Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho
Test Power Reduction with Multiple Capture Orders. Asian Test Symposium (2004)
Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee
Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (3) (2003)
Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng
A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. Asian Test Symposium (2003)
Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee
An efficient BIST method for distributed small buffers. IEEE Trans. Very Large Scale Integr. Syst. 10 (4) (2002)
Wei-Lun Wang, Kuen-Jong Lee
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. J. Electron. Test. 18 (1) (2002)
Kuen-Jong Lee, Chau-chin Su
Guest Editorial. J. Electron. Test. 18 (1) (2002)
Kuen-Jong Lee, Jih-Jeen Chen
Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Asian Test Symposium (2002)
Kuen-Jong Lee, Tsung-Chu Huang
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. J. Electron. Test. 18 (6) (2002)
Yun-Che Wen, Kuen-Jong Lee
Analysis and generation of control and observation structures foranalog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (1) (2001)
Tsung-Chu Huang, Kuen-Jong Lee
Reduction of power consumption in scan-based circuits during testapplication by an input control technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (7) (2001)
Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang
An on-chip march pattern generator for testing embedded memory cores. IEEE Trans. Very Large Scale Integr. Syst. 9 (5) (2001)
Tsung-Chu Huang, Kuen-Jong Lee
A token scan architecture for low power testing. ITC (2001)

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Publication Activity (10 Years)

Top Topics

Top Venues

Kuen-Jong Lee