Tong-Yu Hsieh

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 23

Top Topics

Image Processing

Machine Learning

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

J. Electron. Test.

Publications

Wei-Ji Chao, Tong-Yu Hsieh
Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4. ITC-Asia (2023)
Tong-Yu Hsieh, Chun-Chao Cheng, Wei-Ji Chao, Pin-Xuan Wu
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (4) (2023)
Tong-Yu Hsieh, Pao-Wei Tsui, Jun-Tsung Wu
On No-Reference Error Detection of an Image Stitching System Based on Error-Tolerance. ATS (2022)
Chih-Hao Wang, Natalia Lylina, Ahmed Atteya, Tong-Yu Hsieh, Hans-Joachim Wunderlich
Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. IOLTS (2021)
Tong-Yu Hsieh, Jun-Tsung Wu
Investigation on Error-Tolerability Enhancement of Videos via Re-Encoding for Computer Vision: A Case Study on Object Detection. ICCE-TW (2021)
Tong-Yu Hsieh, Hsin-Yung Shen, Chia-Teng Hsu
Cost-Effective Reliable Edge Computing Hardware Design Based on Module Simplification and Duplication: A Case Study on Vehicle Detection Based on Support Vector Machine. VLSI-DAT (2020)
Chih-Hao Wang, Tong-Yu Hsieh
An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications. ACM Trans. Design Autom. Electr. Syst. 25 (1) (2020)
Tong-Yu Hsieh, Pin-Xuan Wu, Chun-Chao Cheng
On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection. VTS (2020)
Tong-Yu Hsieh, Yu-Min Chung
A Self-Detection and Self-Repair Methodology for Reliable Speech Recognition Considering AWGN Noises. ITC-Asia (2020)
Tong-Yu Hsieh, Chen-Chia Chung, Jun-Tsung Wu
On Enhancing Error-Tolerability of Videos via Re-Encoding with Adaptive I-Frame Insertion. ITC-Asia (2020)
Tong-Yu Hsieh, Kuang-Chun Lin, Hsin-Hsien Lin
A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection. ITC-Asia (2019)
Tong-Yu Hsieh, Yuan-Cheng Lin, Hsin-Yung Shen
On Automatic Generation of Training Images for Machine Learning in Automotive Applications. AICAS (2019)
Tong-Yu Hsieh, Yi-Han Peng, Kuan-Chih Cheng
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (2) (2018)
Chih-Hao Wang, Tong-Yu Hsieh
On Probability of Detection Lossless Concurrent Error Detection Based on Implications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Tong-Yu Hsieh, Shang-En Chan, Chi-Hsuan Ho
On no-reference on-line error-tolerability testing for videos. ETS (2018)
Tong-Yu Hsieh, Chao-Ru Chen
A No-Reference Error-Tolerability Test Methodology for Image Processing Applications. ITC-Asia (2018)
Chih-Hao Wang, Chi-Hsuan Ho, Tong-Yu Hsieh
Error Indication Signal Collapsing for Implication-Based Concurrent Error Detection. ITC-Asia (2018)
Tong-Yu Hsieh, Tai-Ang Cheng, Chao-Ru Chen
Error-Tolerability Evaluation and Test for Images in Face Detection Applications. ATS (2017)
Tong-Yu Hsieh, Kuan-Hsien Li, Chen-Chia Chung
A fault-analysis oriented re-design and cost-effectiveness evaluation methodology for error tolerant applications. Microelectron. J. 66 (2017)
Tong-Yu Hsieh, Tsung-Liang Chih, Mei-Jung Wu
Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 25 (9) (2017)
Chih-Hao Wang, Tong-Yu Hsieh
A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability. ITC-Asia (2017)
Tong-Yu Hsieh, Tai-Ping Wang, Shuo Yang, Chin-An Hsu, Yi-Lung Lin
An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing. IEICE Trans. Electron. (3) (2016)
Tong-Yu Hsieh, Chih-Hao Wang, Tsung-Liang Chih, Ya-Hsiu Chi
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Tong-Yu Hsieh, Yi-Han Peng
Filtering-based error-tolerability evaluation of image processing circuits. IOLTS (2015)
Tong-Yu Hsieh, Chih-Hao Wang, Chun-Wei Kuo, Shu-Yu Huang, Tsung-Liang Chih
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement. J. Electron. Test. 31 (5-6) (2015)
Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh
Output-bit selection with X-avoidance using multiple counters for test-response compaction. ETS (2014)
Tong-Yu Hsieh, Yi-Han Peng, Kuan-Hsien Li
Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation. J. Electron. Test. 30 (6) (2014)
Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng
On efficient error-tolerability evaluation and maximization for image processing applications. VLSI-DAT (2014)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty
Efficient LFSR Reseeding Based on Internal-Response Feedback. J. Electron. Test. 30 (6) (2014)
Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh
Output selection for test response compaction based on multiple counters. VLSI-DAT (2014)
Tong-Yu Hsieh, Yi-Han Peng, Chia-Chi Ku
An Efficient Test Methodology for Image Processing Applications Based on Error-Tolerance. Asian Test Symposium (2013)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty
A New LFSR Reseeding Scheme via Internal Response Feedback. Asian Test Symposium (2013)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu
Counter-Based Output Selection for Test Response Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (1) (2013)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Wee-Lung Ang
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Tong-Yu Hsieh, Chia-Chi Ku, Chia-Hung Yeh
A yield and reliability enhancement framework for image processing applications. APCCAS (2012)
Wei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee
Routing-efficient implementation of an internal-response-based BIST architecture. VLSI-DAT (2012)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. Asian Test Symposium (2012)
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Shih-Shiun Chien, Krishnendu Chakrabarty
Accumulator-based output selection for test response compaction. ISCAS (2012)
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (5) (2012)
Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh
Test Response Compaction via Output Bit Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (10) (2011)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (6) (2011)
Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. IEEE Trans. Very Large Scale Integr. Syst. 18 (7) (2010)
Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee
Tolerance of performance degrading faults for effective yield improvement. ITC (2009)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Trans. Reliab. 57 (1) (2008)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE (2007)
Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You
Test Efficiency Analysis and Improvement of SOC Test Platforms. ATS (2007)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS (2006)
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
A novel test methodology based on error-rate to support error-tolerance. ITC (2005)