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On-Chip SOC Test Platform Design Based on IEEE 1500 Standard.
Kuen-Jong Lee
Tong-Yu Hsieh
Chin-Yao Chang
Yu-Ting Hong
Wen-Cheng Huang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
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high speed
single chip
low cost
rapid prototyping
distributed architecture
case study
user interface
low power
real time
evolvable hardware
design considerations
built in self test
hardware software partitioning
chip design
physical design
circuit design
experimental design
design process
e learning