Tsung-Chu Huang

Publication Activity (10 Years)

Years Active: 1996-2023
Publications (10 Years): 17

Top Topics

Lagrange Interpolation

Confidence Weighted

Top Venues

Publications

Che Lin, Heng Hsu, Tsung-Chu Huang
Redundant Lagrange Interpolation for Fault-Tolerant Winograd Convolution. ICCE-Taiwan (2023)
Ting-Yu Chen, Zong-Yu Wang, Tsung-Chu Huang
TCB Convolution: Ternary-Coded Binarized Convolutions with Fixed-Point Filters. ICCE-Taiwan (2023)
Kuan-Yu Huang, Jettae Schroff, Cheng-Di Tsai, Tsung-Chu Huang
2DAN-BNN: Two-Dimensional AN-Code Decoders for Binarized Neural Networks. ICCE-TW (2022)
Jyun-Xin Ke, Siang-En Ciou, Ting-Yu Chen, Tsung-Chu Huang
SPINDLE: Self-Pretrainable In-situ Normalizer for Deep Learning Error Function. ICCE-TW (2022)
Wan Ju Huang, Hsiao-Wen Fu, Tsung-Chu Huang
AN-HRNS: AN-Coded Hierarchical Residue Number System for Reliable Neural Network Accelerators. ATS (2022)
Ting-Yu Chen, Cheng-Di Tsai, Hsiao-Wen Fu, Yung-Chun Yang, Tsung-Chu Huang
Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics. ICCE-TW (2021)
Cheng-Di Tsai, Ting-Yu Chen, Hsiao-Wen Fu, Tsung-Chu Huang
TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network. AICAS (2021)
Hsiao-Wen Fu, Ting-Yu Chen, Cheng-Di Tsai, Meng-Wei Shen, Tsung-Chu Huang
AN-Coded Redundant Residue Number System for Reliable Neural Networks. ICCE-TW (2021)
Cheng-Di Tsai, Hsiao-Wen Fu, Ting-Yu Chen, Tsung-Chu Huang
TAIWAN Online: Test AI with AN Codes Online for Automotive Chips. ITC-Asia (2021)
Cho-Sheng Lin, Jing Huang, Po-Sheng Chang, Chun-Yen Tsai, Tsung-Chu Huang
SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs. ICCE-TW (2021)
Wen-Chang Yang, Shu-Yun Lin, Tsung-Chu Huang
Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network. ICCE-TW (2020)
Liang-Yu Lin, Jerrae Schroff, Chia-Cheng Liang, Tsung-Chu Huang
Approximate Computing for Batch Learning in Neural Network. ICCE-TW (2020)
Liang-Yu Lin, Jerrae Schroff, Tsu-Ping Lin, Tsung-Chu Huang
Residue Number System Design Automation for Neural Network Acceleration. ICCE-TW (2020)
Tsung-Chu Huang
Self-Checking Residue Number System for Low-Power Reliable Neural Network. ATS (2019)
Tsung-Chu Huang, Chun-Hao Chiang, Mo-Han Lin
Low-Cost and Fast Design of Precise Activation Functions in Neural Network. ICCE-TW (2019)
Tsung-Chu Huang, Jeffae Schroff
Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. ATS (2018)
Tsung-Chu Huang
Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes. IEEE Commun. Lett. 19 (6) (2015)
Tsung-Chu Huang
High-yield performance-efficient redundancy analysis for 2D memory. Sci. China Inf. Sci. 54 (8) (2011)
Tsung-Chu Huang, Kuei-Yeh Lu, Yen-Chieh Huang
HYPERA: High-Yield Performance-Efficient Redundancy Analysis. Asian Test Symposium (2010)
Tsung-Chu Huang
Multi-valued equal-weight codes for self-checking and matching. IEEE Commun. Lett. 13 (12) (2009)
Tsung-Chu Huang
A Low-Power Dependable Berger Code for Fully Asymmetric Communication. IEEE Commun. Lett. 12 (10) (2008)
Tsung-Chu Huang, Gau-Bin Chang, Ling Li
Congruence Synchronous Mirror Delay. ISCAS (2007)
Kuen-Jong Lee, Tsung-Chu Huang
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. J. Electron. Test. 18 (6) (2002)
Tsung-Chu Huang, Kuen-Jong Lee
Reduction of power consumption in scan-based circuits during testapplication by an input control technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (7) (2001)
Tsung-Chu Huang, Kuen-Jong Lee
A token scan architecture for low power testing. ITC (2001)
Tsung-Chu Huang, Kuen-Jong Lee
A Low-Power LFSR Architecture. Asian Test Symposium (2001)
Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen
Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium (2000)
Tsung-Chu Huang, Kuen-Jong Lee
An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Asian Test Symposium (1999)
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. ACM Trans. Design Autom. Electr. Syst. 4 (2) (1999)
Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee
Built-in current sensor designs based on the bulk-driven technique. Asian Test Symposium (1997)
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Asian Test Symposium (1996)