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Test pattern generation and clock disabling for simultaneous test time and power reduction.
Jih-Jeen Chen
Chia-Kai Yang
Kuen-Jong Lee
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2003)
Keyphrases
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power consumption
power reduction
low power
high speed
power saving
low cost
real time
pattern recognition
design process
power dissipation