Ing-Chao Lin

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 31

Top Topics

Efficient Implementation

Machine Learning

Memory Management

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks. CoRR (2024)
Mengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Grace Li Zhang
Class-Aware Pruning for Efficient Neural Networks. DATE (2024)
Yu-Guang Chen, Hsiu-Yi Yang, Ing-Chao Lin
GNN-Based INC and IVC Co-Optimization for Aging Mitigation. ETS (2024)
Yu-Guang Chen, Chieh-Shih Wang, Ing-Chao Lin, Zheng-Wei Chen, Ulf Schlichtmann
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (5) (2024)
Hoang-Hiep Le, Md. Aftab Baig, Wei-Chen Hong, Cheng-Hsien Tsai, Cheng-Jui Yeh, Fu-Xiang Liang, I-Ting Huang, Wei-Tzu Tsai, Ting-Yin Cheng, Sourav De, Nan-Yow Chen, Wen-Jay Lee, Ing-Chao Lin, Da-Wei Chang, Darsen D. Lu
CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials. CoRR (2023)
Mengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Grace Li Zhang
Class-Aware Pruning for Efficient Neural Networks. CoRR (2023)
Wei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing. ICCAD (2023)
Po-Yuan Chen, Fang-Yi Gu, Yu-Hong Huang, Ing-Chao Lin
WRAP: Weight RemApping and Processing in RRAM-based Neural Network Accelerators Considering Thermal Effect. DATE (2022)
Wei Cheng, Chun-Feng Wu, Yuan-Hao Chang, Ing-Chao Lin
GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging. ICCAD (2022)
Wei Cheng, Ing-Chao Lin, Yun-Yang Shih
An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (10) (2022)
Fang-Yi Gu, Ing-Chao Lin, Jia-Wei Lin
A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation. IEEE Access 10 (2022)
Yu-Guang Chen, Chi-Hsu Wang, Ing-Chao Lin
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine. ISOCC (2022)
Ing-Chao Lin, Chi-Huan Tang, Chi-Ting Ni, Xing Hu, Yu-Tong Shen, Pei-Yin Chen, Yuan Xie
A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Jilan Lin, Cheng-Da Wen, Xing Hu, Tianqi Tang, Ing-Chao Lin, Yu Wang, Yuan Xie
Rescuing RRAM-Based Computing From Static and Dynamic Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (10) (2021)
Yu-Guang Chen, Ing-Chao Lin, Yong-Che Wei
A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning. ISQED (2021)
Honggang Yu, Shihfeng Zeng, Teng Zhang, Ing-Chao Lin, Yier Jin
Exploring Adversarial Examples for Efficient Active Learning in Machine Learning Classifiers. CoRR (2021)
Yu-Guang Chen, Ing-Chao Lin, Kun-Wei Chiu, Cheng-Hsuan Liu
-aware wake-up strategy: Concept, design, and manipulation. Integr. 80 (2021)
Yu-Guang Chen, Yu-Yi Lin, Ing-Chao Lin
An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems. ISQED (2020)
Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin
Overview of 2020 CAD Contest at ICCAD. ICCAD (2020)
Ing-Chao Lin, Wei-Ting Chen, Yu-Cheng Chou, Pei-Yin Chen
A Novel Comparison-Free 1-D Median Filter. IEEE Trans. Circuits Syst. II Express Briefs (7) (2020)
Ing-Chao Lin, Da-Wei Chang, Wei-Jun Chen, Jian-Ting Ke, Po-Han Huang
Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (9) (2020)
Ing-Chao Lin, Da-Wei Chang, Chen-Tai Kao, Sheng-Xuan Lin
Infection-Based Dead Page Prediction in Hybrid Memory Architecture. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Yu-Guang Chen, Ing-Chao Lin, Jian-Ting Ke
ROAD: Improving Reliability of Multi-core System via Asymmetric Aging. ICCAD (2019)
Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin
Overview of 2019 CAD Contest at ICCAD. ICCAD (2019)
Da-Wei Chang, Ing-Chao Lin, Yi-Chiao Lin, Wen-Zhi Huang
OCMAS: Online Page Clustering for Multibank Scratchpad Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (2) (2019)
Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration. IEEE Trans. Computers 68 (12) (2019)
Ing-Chao Lin, Yun Kae Law, Yuan Xie
Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes. IEEE Trans. Very Large Scale Integr. Syst. 26 (1) (2018)
Kun-Wei Chiu, Yu-Guang Chen, Ing-Chao Lin
An efficient NBTI-aware wake-up strategy for power-gated designs. DATE (2018)
Yun Kae Law, Ing-Chao Lin, Cheng-Chien Lin
Reducing aging on scratchpad memory using temporal- and FSM-based power management. VLSI-DAT (2017)
Da-Wei Chang, Ing-Chao Lin, Lin-Chun Yong
ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (3) (2017)
Ing-Chao Lin, Yen-Han Lee, Sheng-Wei Wang
Reducing Aging Effects on Ternary CAM. IEICE Trans. Electron. (7) (2016)
Ing-Chao Lin, Yu-Hung Cho, Yi-Ming Yang
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Ing-Chao Lin, Jeng-Nian Chiou
High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Ing-Chao Lin, Yi-Ming Yang, Cheng-Chian Lin
High-Performance Low-Power Carry Speculative Addition With Variable Latency. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Ing-Chao Lin, Kuan-Hui Li, Chia-Hao Lin, Kai-Chiang Wu
NBTI and Leakage Reduction Using ILP-Based Approach. IEEE Trans. Very Large Scale Integr. Syst. 22 (9) (2014)
Ing-Chao Lin, Shun-Ming Syu, Tsung-Yi Ho
NBTI tolerance and leakage reduction using gate sizing. ACM J. Emerg. Technol. Comput. Syst. 11 (1) (2014)
Kai-Chiang Wu, Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (10) (2014)
Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang, Yi-Luen Wu
Analyzing the BTI Effect on Multi-bit Retention Registers. ICS (2014)
Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, Chung-Ping Young
CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Shun-Ming Syu, Yu-Hui Shao, Ing-Chao Lin
High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy. ACM Great Lakes Symposium on VLSI (2013)
Yen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang
Impacts of NBTI and PBTI effects on ternary CAM. ISQED (2013)
Chia-Hao Lin, Ing-Chao Lin
High accuracy approximate multiplier with error correction. ICCD (2013)
Ing-Chao Lin, Chin-Hung Lin, Kuan-Hui Li
Leakage and Aging Optimization Using Transmission Gate-Based Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (1) (2013)
Yu-Hung Cho, Ing-Chao Lin, Yi-Ming Yang
Aging-aware reliable multiplier design. SoCC (2012)
Chin-Hung Lin, Ing-Chao Lin, Kuan-Hui Li
TG-based technique for NBTI degradation and leakage optimization. ISLPED (2011)
Shi-Qun Zheng, Ing-Chao Lin, Yen-Han Lee
Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect. ACM Great Lakes Symposium on VLSI (2011)
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED (2006)
Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan
A power estimation methodology for systemC transaction level models. CODES+ISSS (2005)
Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Des. Autom. Embed. Syst. 10 (2-3) (2005)