Tsung-Wei Huang

ORCID

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 85

Top Venues

ICCAD

DAC

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

HPEC

Publications

Shao-Hung Chan, Zhe Chen, Dian-Lun Lin, Yue Zhang, Daniel Harabor, Tsung-Wei Huang, Sven Koenig, Thomy Phan
Anytime Multi-Agent Path Finding using Operation Parallelism in Large Neighborhood Search. CoRR (2024)
Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang
Heterogeneous Static Timing Analysis with Advanced Delay Calculator. DATE (2024)
Shui Jiang, Rongliang Fu, Lukas Burgholzer, Robert Wille, Tsung-Yi Ho, Tsung-Wei Huang
FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array. ICPP (2024)
Taoran Lu, Peng Yin, Guan-Ming Su, Dae Yeol Lee, Tsung-Wei Huang, Sejin Oh, Sean McCarthy, Walt Husak, Gary J. Sullivan
The Multiplane Image Information SEI Message and its Use for Distribution of Volumetric Video with Conventional Codecs. DCC (2024)
Shao-Hung Chan, Zhe Chen, Dian-Lun Lin, Yue Zhang, Daniel Harabor, Sven Koenig, Tsung-Wei Huang, Thomy Phan
Anytime Multi-Agent Path Finding using Operation Parallelism in Large Neighborhood Search. AAMAS (2024)
Cheng-Hsiang Chiu, Zhicheng Xiong, Zizheng Guo, Tsung-Wei Huang, Yibo Lin
An Efficient Task-Parallel Pipeline Programming Framework. HPC Asia (2024)
Chedi Morchdi, Cheng-Hsiang Chiu, Yi Zhou, Tsung-Wei Huang
A Resource-efficient Task Scheduling System using Reinforcement Learning : Invited Paper. ASPDAC (2024)
Chih-Chun Chang, Boyang Zhang, Tsung-Wei Huang
GSAP: A GPU-Accelerated Stochastic Graph Partitioner. ICPP (2024)
Tsung-Wei Huang, Boyang Zhang, Dian-Lun Lin, Cheng-Hsiang Chiu
Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System. ISPD (2024)
Chih-Chun Chang, Tsung-Wei Huang
uSAP: An Ultra-Fast Stochastic Graph Partitioner. HPEC (2023)
Guannan Guo, Tsung-Wei Huang, Martin D. F. Wong
Fast STA Graph Partitioning Framework for Multi-GPU Acceleration. DATE (2023)
Dian-Lun Lin, Yanqing Zhang, Haoxing Ren, Brucek Khailany, Shih-Hsin Wang, Tsung-Wei Huang
GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs. DAC (2023)
Tsung-Wei Huang, Peihan Tu, Guan-Ming Su
Neural Segmentation Field in 3D Scene. ACSSC (2023)
Tsung-Wei Huang, Guan-Ming Su, Peng Yin
Film Grain Removal Using Metadata. ICIP (2023)
Ying-Yi Hong, Christine Joy E. Arce, Tsung-Wei Huang
A Robust Hybrid Classical and Quantum Model for Short-Term Wind Speed Forecasting. IEEE Access 11 (2023)
Elmir Dzaka, Dian-Lun Lin, Tsung-Wei Huang
Parallel And-Inverter Graph Simulation Using a Task-graph Computing System. IPDPS Workshops (2023)
Ran-Yu Chang, Yu-Chao Hsu, Tsung-Wei Huang
Taiwan Student Quantum Computer Society. QCE (2023)
Cheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang
Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms. ICCAD (2023)
Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang
Invited Paper: Overview of 2023 CAD Contest at ICCAD. ICCAD (2023)
Shui Jiang, Tsung-Wei Huang, Tsung-Yi Ho
GLARE: Accelerating Sparse DNN Inference Kernels with Global Memory Access Reduction. HPEC (2023)
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo, Sushma Yellapragada, Martin D. F. Wong
A GPU-Accelerated Framework for Path-Based Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
Accelerating Static Timing Analysis Using CPU-GPU Heterogeneous Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Tsung-Wei Huang
qTask: Task-parallel Quantum Circuit Simulation with Incrementality. IPDPS (2023)
Shui Jiang, Tsung-Wei Huang, Bei Yu, Tsung-Yi Ho
SNICIT: Accelerating Sparse Neural Network Inference via Compression at Inference Time on GPU. ICPP (2023)
Zizheng Guo, Mingwei Yang, Tsung-Wei Huang, Yibo Lin
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (10) (2022)
Cheng-Hsiang Chiu, Tsung-Wei Huang
Efficient timing propagation with simultaneous structural and pipeline parallelisms: late breaking results. DAC (2022)
Dian-Lun Lin, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang
From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus. ICPP (2022)
Cheng-Hsiang Chiu, Tsung-Wei Huang
Composing Pipeline Parallelism using Control Taskflow Graph. HPDC (2022)
Tsung-Wei Huang, Dian-Lun Lin, Chun-Xun Lin, Yibo Lin
Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System. IEEE Trans. Parallel Distributed Syst. 33 (6) (2022)
Tsung-Wei Huang, Yibo Lin
Concurrent CPU-GPU Task Programming using Modern C++. IPDPS Workshops (2022)
Tsung-Wei Huang
qTask: Task-parallel Quantum Circuit Simulation with Incrementality. CoRR (2022)
Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Kexing Zhou, Zizheng Guo, Tsung-Wei Huang, Yibo Lin
Efficient Critical Paths Search Algorithm using Mergeable Heap. ASP-DAC (2022)
Tsung-Wei Huang, Leslie Hwang
Task-Parallel Programming with Constrained Parallelism. HPEC (2022)
Cheng-Hsiang Chiu, Tsung-Wei Huang, Zizheng Guo, Yibo Lin
Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++. CoRR (2022)
Tsung-Wei Huang, Yibo Lin
Concurrent CPU-GPU Task Programming using Modern C++. CoRR (2022)
Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato
Overview of 2022 CAD Contest at ICCAD. ICCAD (2022)
Tsung-Wei Huang
Enhancing the Performance Portability of Heterogeneous Circuit Analysis Programs. HPEC (2022)
Dian-Lun Lin, Tsung-Wei Huang
Accelerating Large Sparse Neural Network Inference Using GPU Task Graph Parallelism. IEEE Trans. Parallel Distributed Syst. 33 (11) (2022)
Cheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang
An Experimental Study of SYCL Task Graph Parallelism for Large-Scale Machine Learning Workloads. Euro-Par Workshops (2021)
Dian-Lun Lin, Tsung-Wei Huang
Efficient GPU Computation Using Task Graph Parallelism. Euro-Par (2021)
Tsung-Wei Huang, Guan-Ming Su
Revertible Guidance Image Based Image Detail Enhancement. ICIP (2021)
Yasin Zamani, Tsung-Wei Huang
A High-Performance Heterogeneous Critical Path Analysis Framework. HPEC (2021)
Tsung-Wei Huang
Machine Learning System-Enabled GPU Acceleration for EDA. VLSI-DAT (2021)
Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Tsung-Wei Huang
TFProf: Profiling Large Taskflow Programs with Modern D3 and C++. ProTools@SC (2021)
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
GPU-accelerated Path-based Timing Analysis. DAC (2021)
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. DAC (2021)
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
GPU-accelerated Critical Path Generation with Path Constraints. ICCAD (2021)
Tsung-Wei Huang, Guannan Guo, Chun-Xun Lin, Martin D. F. Wong
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
OpenTimer v2: A Parallel Incremental Timing Analysis Engine. IEEE Des. Test 38 (2) (2021)
Kuan-Ming Lai, Tsung-Wei Huang, Pei-Yu Lee, Tsung-Yi Ho
ATM: A High Accuracy Extracted Timing Model for Hierarchical Timing Analysis. ASP-DAC (2021)
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism. ICCAD (2021)
Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato
Overview of 2021 CAD Contest at ICCAD. ICCAD (2021)
McKay Mower, Luke Majors, Tsung-Wei Huang
Taskflow-San: Sanitizing Erroneous Control Flow in Taskflow Graphs. ESPM2@SC (2021)
Wei-Jia Huang, Wei-Chen Chien, Chien-Hung Cho, Che-Chun Huang, Tsung-Wei Huang, Ching-Ray Chang
Mermin's inequalities of multiple qubits with orthogonal measurements on IBM Q 53-qubit system. Quantum Eng. 2 (2) (2020)
Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong
An Efficient Work-Stealing Scheduler for Task Dependency Graph. ICPADS (2020)
Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin
Overview of 2020 CAD Contest at ICCAD. ICCAD (2020)
Guannan Guo, Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints. DAC (2020)
Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin
Cpp-Taskflow v2: A General-purpose Parallel and Heterogeneous Task Programming System at Scale. CoRR (2020)
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
GPU-Accelerated Static Timing Analysis. ICCAD (2020)
Tsung-Wei Huang
A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD. ICCAD (2020)
Dian-Lun Lin, Tsung-Wei Huang
A Novel Inference Algorithm for Large Sparse Neural Network using Task Graph Parallelism. HPEC (2020)
Tsung-Wei Huang
Programming Systems for Parallelizing VLSI CAD and Beyond. VLSI-DAT (2020)
Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
Cpp-Taskflow: Fast Task-Based Parallel Programming Using Modern C++. IPDPS (2019)
Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong
An Efficient and Composable Parallel Task Programming Library. HPEC (2019)
Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong
A Modern C++ Parallel Task Programming Library. ACM Multimedia (2019)
Tsung-Wei Huang, Jenq-Neng Hwang, Suzanne Romain, Farron Wallace
Recognizing Fish Species Captured Live on Wild Sea Surface in Videos by Deep Metric Learning with a Temporal Constraint. ICIP (2019)
Kuan-Ming Lai, Tsung-Wei Huang, Tsung-Yi Ho
A General Cache Framework for Efficient Generation of Timing Critical Paths. DAC (2019)
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
Distributed Timing Analysis at Scale. DAC (2019)
Tsung-Wei Huang, Jiarui Cai, Hao Yang, Hung-Min Hsu, Jenq-Neng Hwang
Multi-View Vehicle Re-Identification using Temporal Attention Model and Metadata Re-ranking. CVPR Workshops (2019)
Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
Essential Building Blocks for Creating an Open-source EDA Project. DAC (2019)
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
DtCraft: A High-Performance Distributed Execution Engine at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Tsung-Wei Huang, Jenq-Neng Hwang, Suzanne Romain, Farron Wallace
Fish Tracking and Segmentation From Stereo Videos on the Wild Sea Surface for Electronic Monitoring of Rail Fishing. IEEE Trans. Circuits Syst. Video Technol. 29 (10) (2019)
Hung-Min Hsu, Tsung-Wei Huang, Gaoang Wang, Jiarui Cai, Zhichao Lei, Jenq-Neng Hwang
Multi-Camera Tracking of Vehicles based on Deep Features Re-ID and Trajectory-Based Camera Link Models. CVPR Workshops (2019)
Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
A General-purpose Distributed Programming System using Data-parallel Streams. ACM Multimedia (2018)
Chun-Xun Lin, Tsung-Wei Huang, Ting Yu, Martin D. F. Wong
A Distributed Power Grid Analysis Framework from Sequential Stream Graph. ACM Great Lakes Symposium on VLSI (2018)
Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong
Routing at compile time. ISQED (2018)
Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong
MtDetector: A High-performance Marine Traffic Detector at Stream Scale. DEBS (2018)
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
DtCraft: A distributed execution engine for compute-intensive applications. ICCAD (2017)
Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong
LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs. DAC (2017)
Tsung-Wei Huang, Jenq-Neng Hwang, Suzanne Romain, Farron Wallace
Live Tracking of Rail-Based Fish Catching on Wild Sea Surface. CVAUI@ICPR (2016)
Tsung-Wei Huang, Jenq-Neng Hwang, Craig S. Rose
Chute based automated fish length measurement and water drop detection. ICASSP (2016)
Tsung-Wei Huang, Martin D. F. Wong
UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (11) (2016)
Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran
A distributed timing analysis framework for large designs. DAC (2016)
Tsung-Wei Huang, Martin D. F. Wong
Accelerated Path-Based Timing Analysis with MapReduce. ISPD (2015)
Tsung-Wei Huang, Martin D. F. Wong
OpenTimer: A High-Performance Timing Analysis Tool. ICCAD (2015)
Tsung-Wei Huang, Martin D. F. Wong
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. SLIP (2015)
Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
UI-timer: an ultra-fast clock network pessimism removal algorithm. ICCAD (2014)
Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
UI-route: An ultra-fast incremental maze routing algorithm. SLIP (2014)
Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
Fast path-based timing analysis for CPPR. ICCAD (2014)
Sheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Shang-Tsung Yu, Tsung-Yi Ho
Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (9) (2014)
Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho
Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (2) (2013)
Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho
An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Ying-Han Chen, Chung-Lun Hsu, Li-Chen Tsai, Tsung-Wei Huang, Tsung-Yi Ho
A Reliability-Oriented Placement Algorithm for Reconfigurable Digital Microfluidic Biochips Using 3-D Deferred Decision Making Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho
An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chips. ASP-DAC (2012)
Tsung-Wei Huang, Jia-Wen Chang, Tsung-Yi Ho
Integrated fluidic-chip co-design methodology for digital microfluidic biochips. ISPD (2012)
Sheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho
Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips. ICCAD (2012)
Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho
A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (12) (2011)
Tsung-Wei Huang, Yan-You Lin, Jia-Wen Chang, Tsung-Yi Ho
Recent research and emerging challenges in design and optimization for digital microfluidic biochips. SoCC (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

Tsung-Wei Huang