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Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips.
Sheng-Han Yeh
Jia-Wen Chang
Tsung-Wei Huang
Shang-Tsung Yu
Tsung-Yi Ho
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
Keyphrases
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high speed
chip design
low cost
data driven
power system
circuit design
physical design
evolvable hardware
functional verification
case study