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Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips.

Sheng-Han YehJia-Wen ChangTsung-Wei HuangShang-Tsung YuTsung-Yi Ho
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
Keyphrases
  • high speed
  • chip design
  • low cost
  • data driven
  • power system
  • circuit design
  • physical design
  • evolvable hardware
  • functional verification
  • case study