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Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips.
Sheng-Han Yeh
Jia-Wen Chang
Tsung-Wei Huang
Tsung-Yi Ho
Published in:
ICCAD (2012)
Keyphrases
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high speed
chip design
case study
design process
low power
low cost
data driven
high density
evolvable hardware