Kai-Chiang Wu

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 45

Top Topics

Sensor Placement

Matrix Multiplication

Neural Architecture

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods. VTS (2024)
Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. WACV (2024)
Shiuhpyng Winston Shieh, Jeffrey M. Voas, Phil Laplante, Jason W. Rupe, Christian K. Hansen, Yu-Sung Wu, Yi-Ting Chen, Chi-Yu Li, Kai-Chiang Wu
Reliability Engineering in a Time of Rapidly Converging Technologies. IEEE Trans. Reliab. 73 (1) (2024)
Chi-Chih Chang, Wei-Cheng Lin, Chien-Yu Lin, Chong-Yan Chen, Yu-Fang Hu, Pei-Shuo Wang, Ning-Chi Huang, Luis Ceze, Kai-Chiang Wu
Palu: Compressing KV-Cache with Low-Rank Projection. CoRR (2024)
Chia-Heng Yen, Jung-Che Tsai, Kai-Chiang Wu
Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques. ISQED (2023)
Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information. ITC (2023)
Yu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao
Test Generation for Defect-Based Faults of Scan Flip-Flops. VTS (2023)
Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
Outlier Detection for Analog Tests Using Deep Learning Techniques. VTS (2023)
Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. CoRR (2023)
Chi-Chih Chang, Wei-Cheng Lin, Pei-Shuo Wang, Sheng-Feng Yu, Yu-Chen Lu, Kuan-Cheng Lin, Kai-Chiang Wu
Q-YOLOP: Quantization-Aware You Only Look Once for Panoptic Driving Perception. ICME Workshops (2023)
Endri Taka, Aman Arora, Kai-Chiang Wu, Diana Marculescu
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine. CoRR (2023)
Endri Taka, Aman Arora, Kai-Chiang Wu, Diana Marculescu
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine. ICFPT (2023)
Ning-Chi Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu
Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators. ISQED (2023)
Chi-Chih Chang, Wei-Cheng Lin, Pei-Shuo Wang, Sheng-Feng Yu, Yu-Chen Lu, Kuan-Cheng Lin, Kai-Chiang Wu
Q-YOLOP: Quantization-aware You Only Look Once for Panoptic Driving Perception. CoRR (2023)
Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, Mango C.-T. Chao
Rule Generation for Classifying SLT Failed Parts. VTS (2022)
Dong-Zhen Lee, Ying-Yen Chen, Kai-Chiang Wu, Mango C.-T. Chao
Improving Cell-Aware Test for Intra-Cell Short Defects. DATE (2022)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Ning-Chi Huang, Chao-Wei Cheng, Kai-Chiang Wu
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs. IEEE Trans. Very Large Scale Integr. Syst. 30 (1) (2022)
Shuo-Wen Chang, Yu-Teng Nien, Yu-Pang Hu, Kai-Chiang Wu, Chi Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao
Test Methodology for Defect-Based Bridge Faults. IEEE Trans. Very Large Scale Integr. Syst. 30 (7) (2022)
Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS (2021)
Ning-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, Kai-Chiang Wu
An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention. VTS (2021)
Li-Wei Chen, Wei-Chun Wang, Shao-Han Ko, Chien-Yu Chen, Chih-Ting Hsu, Fu-Ching Chiao, Tse-Wei Chen, Kai-Chiang Wu, Hao-Wu Lin
Highly Uniform All-Vacuum-Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing. Adv. Intell. Syst. 3 (1) (2021)
Samuel Liu, Jen-Ho Kuo, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, M.-H. Yang, Kai-Chiang Wu
ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. VLSI-DAT (2021)
Chia-Hsiang Liu, Yu-Shin Han, Yuan-Yao Sung, Yi Lee, Hung-Yueh Chiang, Kai-Chiang Wu
FOX-NAS: Fast, On-device and Explainable Neural Architecture Search. CoRR (2021)
Chia-Hsiang Liu, Yu-Shin Han, Yuan-Yao Sung, Yi Lee, Hung-Yueh Chiang, Kai-Chiang Wu
FOX-NAS: Fast, On-device and Explainable Neural Architecture Search. ICCVW (2021)
Xiao Hu, Ming-Ching Chang, Yuwei Chen, Rahul Sridhar, Zhenyu Hu, Yunhe Xue, Zhenyu Wu, Pengcheng Pi, Jiayi Shen, Jianchao Tan, Xiangru Lian, Ji Liu, Zhangyang Wang, Chia-Hsiang Liu, Yu-Shin Han, Yuan-Yao Sung, Yi Lee, Kai-Chiang Wu, Wei-Xiang Guo, Rick Lee, Shengwen Liang, Zerun Wang, Guiguang Ding, Gang Zhang, Teng Xi, Yubei Chen, Han Cai, Ligeng Zhu, Zhekai Zhang, Song Han, Seonghwan Jeong, YoungMin Kwon, Tianzhe Wang, Jeffery Pan
The 2020 Low-Power Computer Vision Challenge. AICAS (2021)
Li-Wei Chen, Wei-Chun Wang, Shao-Han Ko, Chien-Yu Chen, Chih-Ting Hsu, Fu-Ching Chiao, Tse-Wei Chen, Kai-Chiang Wu, Hao-Wu Lin
Highly Uniform All-Vacuum-Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing. Adv. Intell. Syst. 3 (1) (2021)
Tien-Hung Tseng, Chung-Han Chou, Kai-Chiang Wu
Making Aging Useful by Recycling Aging-induced Clock Skew. ACM Trans. Design Autom. Electr. Syst. 25 (2) (2020)
Yu-Pang Hu, Shuo-Wen Chang, Kai-Chiang Wu, Chi Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao
Test Methodology for Defect-based Bridge Faults. ITC-Asia (2020)
Shu-Ming Liu, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, Ming-Xue Yang, Kai-Chiang Wu
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator. VLSI-DAT (2020)
Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS (2020)
Hao-Chun Chang, Li-An Huang, Kai-Chiang Wu, Yu-Guang Chen
Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience. ISPD (2020)
Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee
Layout-Based Dual-Cell-Aware Tests. VTS (2019)
Kai-Chiang Wu, Wei-Tao Huang, Chiao-Yang Huang
ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience. IOLTS (2019)
Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. ISVLSI (2019)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC (2019)
Ning-Chi Huang, Szu-Ying Chen, Kai-Chiang Wu
Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications. DATE (2019)
Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang
Aging-aware chip health prediction adopting an innovative monitoring strategy. ASP-DAC (2019)
Kai-Chiang Wu, Tien-Hung Tseng, Shou-Chun Li
MAUI: Making aging useful, intentionally. DATE (2018)
Tien-Hung Tseng, Shou-Chun Li, Kai-Chiang Wu
Lifetime Reliability Trojan Based on Exploring Malicious Aging. ATS (2018)
Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang
Sensor-Based Time Speculation in the Presence of Timing Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, Kai-Chiang Wu
Analysis and optimization of variable-latency designs in the presence of timing variability. DATE (2017)
Tien-Hung Tseng, Shu-Sheng Wang, Jian-You Chen, Kai-Chiang Wu
Workload-aware lifetime Trojan based on statistical aging manipulation. DSC (2017)
Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao
Fast WAT test structure for measuring Vt variance based on latch-based comparators. VTS (2017)
Ing-Chao Lin, Kuan-Hui Li, Chia-Hao Lin, Kai-Chiang Wu
NBTI and Leakage Reduction Using ILP-Based Approach. IEEE Trans. Very Large Scale Integr. Syst. 22 (9) (2014)
Kai-Chiang Wu, Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (10) (2014)
Kai-Chiang Wu, Diana Marculescu
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Kai-Chiang Wu, Diana Marculescu
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms. DATE (2012)
Kai-Chiang Wu, Diana Marculescu
Aging-aware timing analysis and optimization considering path sensitization. DATE (2011)
Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. ISLPED (2011)
Kai-Chiang Wu, Diana Marculescu
Clock skew scheduling for soft-error-tolerant sequential circuits. DATE (2010)
Kai-Chiang Wu, Diana Marculescu
Joint logic restructuring and pin reordering against NBTI-induced performance degradation. DATE (2009)
Kai-Chiang Wu, Diana Marculescu
Soft error rate reduction using redundancy addition and removal. ASP-DAC (2008)
Kai-Chiang Wu, Diana Marculescu
Power-aware soft error hardening via selective voltage scaling. ICCD (2008)
Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marculescu
Process variability-aware transient fault modeling and analysis. ICCAD (2008)
Shyh-Leh Chen, Kai-Chiang Wu
Contouring Control of Smooth Paths for Multiaxis Motion Systems Based on Equivalent Errors. IEEE Trans. Control. Syst. Technol. 15 (6) (2007)
Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang
Delay variation tolerance for domino circuits. ASP-DAC (2006)
Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu
Re-synthesis for delay variation tolerance. DAC (2004)