Ning-Chi Huang

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 11

Top Topics

Matrix Completion

Low Rank Matrices

Top Venues

Publications

Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. WACV (2024)
Chi-Chih Chang, Wei-Cheng Lin, Chien-Yu Lin, Chong-Yan Chen, Yu-Fang Hu, Pei-Shuo Wang, Ning-Chi Huang, Luis Ceze, Kai-Chiang Wu
Palu: Compressing KV-Cache with Low-Rank Projection. CoRR (2024)
Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. CoRR (2023)
Ning-Chi Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu
Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators. ISQED (2023)
Ning-Chi Huang, Chao-Wei Cheng, Kai-Chiang Wu
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs. IEEE Trans. Very Large Scale Integr. Syst. 30 (1) (2022)
Ning-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, Kai-Chiang Wu
An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention. VTS (2021)
Samuel Liu, Jen-Ho Kuo, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, M.-H. Yang, Kai-Chiang Wu
ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. VLSI-DAT (2021)
Shu-Ming Liu, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, Ming-Xue Yang, Kai-Chiang Wu
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator. VLSI-DAT (2020)
Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. ISVLSI (2019)
Ning-Chi Huang, Szu-Ying Chen, Kai-Chiang Wu
Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications. DATE (2019)
Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, Kai-Chiang Wu
Analysis and optimization of variable-latency designs in the presence of timing variability. DATE (2017)