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Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs.
Ning-Chi Huang
Yu-Guang Chen
Kai-Chiang Wu
Published in:
ISVLSI (2019)
Keyphrases
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power consumption
real time
evolutionary algorithm
response time
prefetching
high efficiency
design space exploration
training set
computational efficiency