Shu-Yi Kao

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 9

Top Topics

Using Artificial Neural Networks

Behavioral Model

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS (2021)
Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS (2020)
Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee
Layout-Based Dual-Cell-Aware Tests. VTS (2019)
Yi-Cheng Zhao, Yu-Chieh Lin, Ting-Chi Wang, Ting-Hsiung Wang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao
. DATE (2019)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC (2019)
Ling-Yen Song, Chun Wang, Chien-Nan Jimmy Liu, Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
Non-regression approach for the behavioral model generator in mixed-signal system verification. VLSI-SoC (2017)
Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao
Case study of process and design performance debugging with Digital Speed Sensor. VLSI-DAT (2015)