Jih-Nung Lee

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 10

Top Topics

Using Artificial Neural Networks

Robust Estimator

Friction Coefficient

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IET Comput. Digit. Tech.

Publications

Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS (2021)
Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS (2020)
Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee
Layout-Based Dual-Cell-Aware Tests. VTS (2019)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC (2019)
Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao
Measurement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao
Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques. ASP-DAC (2017)
Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien, Ying-Yen Chen, Max Wu, Jih-Nung Lee, Mango C.-T. Chao
Methodology of generating dual-cell-aware tests. VTS (2017)
Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique. VTS (2016)
Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao
Case study of process and design performance debugging with Digital Speed Sensor. VLSI-DAT (2015)
Po-Juei Chen, Chieh-Chih Che, J. C.-M. Li, Shuo-Fen Kuo, Pei-Ying Hsueh, Chun-Yi Kuo, Jih-Nung Lee
Physical-aware systematic multiple defect diagnosis. IET Comput. Digit. Tech. 8 (5) (2014)
Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu
Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT (2013)
Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu
A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. ITC (2009)
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
Fault Pattern Oriented Defect Diagnosis for Memories. ITC (2003)
Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD (2003)