A hybrid self-testing methodology of processor cores.

Tai-Hua Lu Chung-Ho Chen Kuen-Jong Lee

Published in: ISCAS (2008)

Keyphrases

multi core processors
processor core
high speed
test cases
test set
neural network
parallel architectures
real time
information systems
low cost
level parallelism
multi core systems
model based testing
single chip
high end
hybrid learning
test data
general purpose
genetic algorithm