Mark Kassab

Publication Activity (10 Years)

Years Active: 1995-2022
Publications (10 Years): 8

Top Topics

Hierarchical Decomposition

Ibm Zenterprise

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS (2022)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia (2020)
Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
Effective Design of Layout-Friendly EDT Decompressor. VTS (2020)
Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. ITC (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC (2020)
Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS (2019)
Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski
Hybrid Hierarchical and Modular Tests for SoC Designs. NATW (2015)
Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
Isometric test compression with low toggling activity. ITC (2014)
Xijiang Lin, Mark Kassab, Janusz Rajski
Using dynamic shift to reduce test data volume in high-compression designs. ETS (2014)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW (2014)
Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
EDT bandwidth management - Practical scenarios for large SoC designs. ITC (2013)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab
A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. ITC (2011)
Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC (2011)
Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
Low capture power at-speed test in EDT environment. ITC (2010)
Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
Dynamic channel allocation for higher EDT compression in SoC designs. ITC (2010)
Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC (2010)
Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab
At-speed scan test with low switching activity. VTS (2010)
Xijiang Lin, Mark Kassab
Test Generation for Designs with On-Chip Clock Generators. Asian Test Symposium (2009)
Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low Power Scan Shift and Capture in the EDT Environment. ITC (2008)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (1) (2008)
Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. 24 (5) (2007)
Xijiang Lin, Mark Kassab, Janusz Rajski
Test Generation for Timing-Critical Transition Faults. ATS (2007)
Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
Test Generation in the Presence of Timing Exceptions and Constraints. DAC (2007)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
X-Press Compactor for 1000x Reduction of Test Data. ITC (2006)
Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
OCI: Open Compression Interface. ITC (2006)
Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo
At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS (2006)
Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS (2006)
Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
Realizing High Test Quality Goals with Smart Test Resource Usage. ITC (2004)
Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (5) (2004)
Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC (2004)
Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC (2003)
Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. 20 (5) (2003)
Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC (2002)
Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
Logic BIST for large industrial designs: real issues and case studies. ITC (1999)
Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC (1998)
Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC (1995)
Mark Kassab, Janusz Rajski, Jerzy Tyszer
Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC (1995)