Aiman H. El-Maleh

Publication Activity (10 Years)

Years Active: 1995-2022
Publications (10 Years): 14

Top Topics

Binary Particle Swarm Optimization

Fault Tolerance

Integrated Circuit

Top Venues

IET Comput. Digit. Tech.

Microelectron. Reliab.

Publications

Mahmoud Habboush, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Saleh AlSaleh
DE-ZFP: An FPGA implementation of a modified ZFP compression/decompression algorithm. Microprocess. Microsystems 90 (2022)
Aiman H. El-Maleh, Ghashmi H. Bin Talib
Time redundancy and gate sizing soft error-tolerant based adder design. Integr. 78 (2021)
Ahmad T. Sheikh, Aiman H. El-Maleh
Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits. J. Circuits Syst. Comput. 27 (6) (2018)
Aiman H. El-Maleh
A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization. Integr. 56 (2017)
Aiman H. El-Maleh
Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits. IET Comput. Digit. Tech. 11 (4) (2017)
Ahmad T. Sheikh, Aiman H. El-Maleh
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing. Integr. 58 (2017)
Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Sadiq M. Sait
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Sadiq M. Sait, Abubakar Bala, Aiman H. El-Maleh
Cuckoo search based resource optimization of datacenters. Appl. Intell. 44 (3) (2016)
Aiman H. El-Maleh
Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits. IET Comput. Digit. Tech. 10 (1) (2016)
Mohammad Alshayeb, Muhammad E. S. Elrabaa, Ayman Hroub, Amran Al-Aghbari, Aiman H. El-Maleh, Abdelhafid Bouhraoua
Towards a Test Definition Language for Integrated Circuits. J. Circuits Syst. Comput. 24 (3) (2015)
Aiman H. El-Maleh
A sequential circuit fault tolerance technique with enhanced area and power. ISSPIT (2015)
Aiman H. El-Maleh, Khaled A. Daud
Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits. IEEE Trans. Reliab. 64 (3) (2015)
Aiman H. El-Maleh
State assignment for power optimization of sequential circuits based on a probabilistic pairwise swap search algorithm. ISSPIT (2015)
Aiman H. El-Maleh, Sadiq M. Sait, Abubakar Bala
State assignment for area minimization of sequential circuits based on cuckoo search optimization. Comput. Electr. Eng. 44 (2015)
Aiman H. El-Maleh, Ayed S. Al-Qahtani
A finite state machine based fault tolerance technique for sequential circuits. Microelectron. Reliab. 54 (3) (2014)
Aiman H. El-Maleh, Feras Chikh Oughali
A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits. Microelectron. Reliab. 54 (1) (2014)
Aiman H. El-Maleh, Feras Chikh Oughali
Enhancing Reliability of Combinational Circuits against Soft Errors by Using a Generalized Modular Redundancy Scheme. ISED (2013)
Aiman H. El-Maleh, Ahmad T. Sheikh, Sadiq M. Sait
Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits. Appl. Soft Comput. 13 (12) (2013)
Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman H. El-Maleh
A scheme of test data compression based on coding of even bits marking and selective output inversion. Comput. Electr. Eng. 36 (5) (2010)
Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani
Reconfigurable broadcast scan compression using relaxation-based test vector decomposition. IET Comput. Digit. Tech. 3 (2) (2009)
Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, Farhan Khan
-transistor structure for reliable nanoelectronic designs. IET Comput. Digit. Tech. 3 (6) (2009)
Aiman H. El-Maleh
Efficient test compression technique based on block merging. IET Comput. Digit. Tech. 2 (5) (2008)
Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki
Transistor-level based defect tolerance for reliable nanoelectronics. AICCSA (2008)
Aiman H. El-Maleh
Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Comput. Digit. Tech. 2 (3) (2008)
Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani
A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos. ATS (2007)
Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Aiman H. El-Maleh, Sadiq M. Sait, F. Nawaz Khan
Finite state machine state assignment for area and power minimization. ISCAS (2006)
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
Evolutionary algorithms for VLSI multi-objective netlist partitioning. Eng. Appl. Artif. Intell. 19 (3) (2006)
Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. Asian Test Symposium (2005)
Aiman H. El-Maleh, Khaled Al-Utaibi
An efficient test relaxation technique for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (6) (2004)
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
General iterative heuristics for VLSI multiobjective partitioning. ISCAS (5) (2003)
Yahya E. Osais, Aiman H. El-Maleh
A static test compaction technique for combinational circuits based on independent fault clustering. ICECS (2003)
Aiman H. El-Maleh, Khaled Al-Utaibi
On efficient extraction of partially specified test sets for synchronous sequential circuits. ISCAS (5) (2003)
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. ISCAS (5) (2003)
Aiman H. El-Maleh, Khaled Al-Utaibi
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. VTS (2003)
Aiman H. El-Maleh
A hybrid test compression technique for efficient testing of systems-on-a-chip. ICECS (2003)
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
Enhancing performance of iterative heuristics for VLSI netlist partitioning. ICECS (2003)
Aiman H. El-Maleh, Yahya E. Osais
Test vector decomposition-based static compaction algorithms for combinational circuits. ACM Trans. Design Autom. Electr. Syst. 8 (4) (2003)
Aiman H. El-Maleh, Raslan H. Al-Abaji
Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression. ICECS (2002)
Aiman H. El-Maleh, Yahya E. Osais
A retiming-based test pattern generator design for built-in self test of data path architectures. ISCAS (4) (2001)
Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. ICCD (2001)
Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC (1998)
Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (5) (1997)
Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
A complexity analysis of sequential ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (11) (1996)
Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
On Test Set Preservation of Retimed Circuits. DAC (1995)
Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly
Testability Implications of Performance-Driven Logic Synthesis. IEEE Des. Test Comput. 12 (2) (1995)
Aiman H. El-Maleh, Janusz Rajski
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (5) (1995)