A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy.
Ahmad T. SheikhAiman H. El-MalehMuhammad E. S. ElrabaaSadiq M. SaitPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
- fault tolerance
- logic circuits
- high speed
- fault tolerant
- low power
- power dissipation
- circuit design
- asynchronous circuits
- load balancing
- distributed systems
- response time
- power consumption
- floating gate
- high availability
- distributed computing
- peer to peer
- replicated databases
- mobile agents
- group communication
- low cost
- fault management
- database replication
- high performance computing
- error detection
- failure recovery
- integrated circuit
- database
- expert systems