Janusz Rajski

ORCID

Publication Activity (10 Years)

Years Active: 1980-2024
Publications (10 Years): 51

Top Venues

ITC

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ETS

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
B: Crypto Hash Functions Based on Hybrid Ring Generators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
Generation of Two-Cycle Tests for Structurally Similar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test 41 (4) (2024)
Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
Hybrid Ring Generators for In-System Test Applications. ETS (2023)
Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
X-Masking for Deterministic In-System Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
A Lightweight True Random Number Generator for Root of Trust Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
DIST: Deterministic In-System Test with X-masking. ITC (2022)
Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
Hardware Root of Trust for SSN-basedDFT Ecosystems. ITC (2022)
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
Test Generation for an Iterative Design Flow with RTL Changes. ITC (2022)
Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
X-Masking for In-System Deterministic Test. ETS (2022)
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
Fast Test Generation for Structurally Similar Circuits. VTS (2022)
Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
LBIST for Automotive ICs With Enhanced Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS (2022)
Bartosz Grzelak, Martin Keim, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
Convolutional Compaction-Based MRAM Fault Diagnosis. ETS (2021)
Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
On Reduction of Deterministic Test Pattern Sets. ITC (2021)
Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. IEEE Trans. Very Large Scale Integr. Syst. 29 (8) (2021)
Friedrich Hapke, Will Howell, Peter C. Maxwell, Edward Brazil, Srikanth Venkataraman, Rudrajit Dutta, Andreas Glowatz, Anja Fast, Janusz Rajski
Defect-Oriented Test: Effectiveness in High Volume Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (3) (2021)
Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
Test Sequence-Optimized BIST for Automotive Applications. ETS (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia (2020)
Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
Effective Design of Layout-Friendly EDT Decompressor. VTS (2020)
Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. ITC (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS (2020)
Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak
X-Tolerant Tunable Compactor for In-System Test. ITC (2020)
Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
Low Cost Hypercompression of Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
Scan Integrity Tests for EDT Compression. IEEE Des. Test 37 (4) (2020)
Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (8) (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC (2020)
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
On Cyclic Scan Integrity Tests for EDT-based Compression. VTS (2019)
Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki
Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC (2019)
Janusz Rajski, Jerzy Tyszer, Justyna Zawada
On New Class of Test Points and Their Applications. ITC (2018)
Will Howell, Friedrich Hapke, Edward Brazil, Srikanth Venkataraman, R. Datta, Andreas Glowatz, Wilfried Redemund, J. Schmerberg, Anja Fast, Janusz Rajski
DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies. ITC (2018)
Michael Chen, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
Hardware Protection via Logic Locking Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer
Staggered ATPG with capture-per-cycle observation test points. VTS (2018)
Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
Deterministic Stellar BIST for In-System Automotive Test. ITC (2018)
Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
Hypercompression of Test Patterns. ITC (2018)
Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
Full-scan LBIST with capture-per-cycle hybrid test points. ITC (2017)
Artur Pogiel, Janusz Rajski, Jerzy Tyszer
) test algorithms. ETS (2017)
Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada
Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
Trimodal Scan-Based Test Paradigm. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (4) (2017)
Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
Test point insertion in hybrid test compression/LBIST architectures. ITC (2016)
Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
On New Test Points for Compact Cell-Aware Tests. IEEE Des. Test 33 (6) (2016)
Nilanjan Mukherjee, Janusz Rajski
Digital Testing of ICs for Automotive Applications. VLSI Design (2016)
Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer
Minimal area test points for deterministic patterns. ITC (2016)
Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
On Test Points Enhancing Hardware Security. ATS (2016)
Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
Transistor stuck-on fault detection tests for digital CMOS circuits. ETS (2016)
Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. ATS (2015)
Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSI Design (2015)
Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada
Design for low test pattern counts. DAC (2015)
Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
A deterministic BIST scheme based on EDT-compressed test patterns. ITC (2015)
Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
Embedded deterministic test points for compact cell-aware tests. ITC (2015)
Janusz Rajski, Nilanjan Mukherjee
Innovative practices session 11C: Advanced scan methodologies [3 presentations]. VTS (2015)
Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS (2015)
Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski
Hybrid Hierarchical and Modular Tests for SoC Designs. NATW (2015)
Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Kun-Han Tsai, Janusz Rajski
Clock-domain-aware test for improving pattern compression. VLSI-DAT (2015)
Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
Isometric test compression with low toggling activity. ITC (2014)
Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast
Cell-Aware Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (9) (2014)
Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada
Quality assurance in memory built-in self-test tools. DDECS (2014)
Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS (2014)
Xijiang Lin, Mark Kassab, Janusz Rajski
Using dynamic shift to reduce test data volume in high-compression designs. ETS (2014)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
On Using Implied Values in EDT-based Test Compression. DAC (2014)
Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? VTS (2014)
Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW (2014)
Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low Power Test Compression with Programmable Broadcast-Based Control. ATS (2014)
Friedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, Juergen Schloeffel, Wilfried Redemund, Andreas Glowatz, Anja Fast, Janusz Rajski
Cell-aware experiences in a high-quality automotive test suite. ETS (2014)
Janusz Rajski, Jerzy Tyszer
Fault diagnosis of TSV-based interconnects in 3-D stacked designs. ITC (2013)
Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
EDT bandwidth management - Practical scenarios for large SoC designs. ITC (2013)
Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC (2013)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. Asian Test Symposium (2013)
Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
New test compression scheme based on low power BIST. ETS (2013)
Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang
On the generation of compact test sets. ITC (2013)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
On Deploying Scan Chains for Data Storage in Test Compression Environment. IEEE Des. Test 30 (1) (2013)
Dariusz Czysz, Janusz Rajski, Jerzy Tyszer
Low power test application with selective compaction in VLSI designs. ITC (2012)
Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
Low power programmable PRPG with enhanced fault coverage gradient. ITC (2012)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
Test generator with preselected toggling for low power built-in self-test. VTS (2012)
Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski
Bandwidth-aware test compression logic for SoC designs. ETS (2012)
Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski
Cell-aware Production test results from a 32-nm notebook processor. ITC (2012)
Xijiang Lin, Janusz Rajski
On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium (2012)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Reduced ATE Interface for High Test Data Compression. ETS (2011)
Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers
Cell-aware analysis for small-delay effects and production test results from different fault models. ITC (2011)
Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer
Ring Generator: An Ultimate Linear Feedback Shift Register. Computer 44 (6) (2011)
Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC (2011)
Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (7) (2011)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium (2011)
Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
Power Aware Embedded Test. Asian Test Symposium (2011)
Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. ETS (2011)
Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy
Low power compression utilizing clock-gating. ITC (2011)
Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

Janusz Rajski