Irith Pomeranz

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 183

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Very Large Scale Integr. Syst.

ACM Trans. Design Autom. Electr. Syst.

VTS

Publications

Subashini Gopalsamy, Irith Pomeranz
A Storage Based LBIST Scheme for Logic Diagnosis. VTS (2024)
Irith Pomeranz
Functional Compaction for Functional Test Sequences. IEEE Access 12 (2024)
Irith Pomeranz
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve. IEEE Trans. Very Large Scale Integr. Syst. 32 (4) (2024)
Irith Pomeranz
Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (1) (2024)
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
Generation of Two-Cycle Tests for Structurally Similar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Irith Pomeranz
Conventional Tests for Approximate Scan Logic. IEEE Des. Test 41 (3) (2024)
Irith Pomeranz
Testability Evaluation for Local Design Modifications. IEEE Trans. Very Large Scale Integr. Syst. 32 (1) (2024)
Irith Pomeranz
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences. ACM Trans. Design Autom. Electr. Syst. 29 (3) (2024)
Irith Pomeranz
Reduced On-chip Storage of Seeds for Built-in Test Generation. ACM Trans. Design Autom. Electr. Syst. 29 (3) (2024)
Irith Pomeranz
Longest Path Selection Based on Path Identifiers. IEEE Access 12 (2024)
Irith Pomeranz
Sharing of Topped-Off Compressed Test Sets Among Logic Blocks. IEEE Access 12 (2024)
Irith Pomeranz
Test Compaction Using (k, 1)-Cycle Tests. VTS (2024)
Irith Pomeranz
Test Insertion for Dynamic Test Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Irith Pomeranz
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults. IEEE Trans. Very Large Scale Integr. Syst. 31 (11) (2023)
Irith Pomeranz
Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Irith Pomeranz
Path Unselection for Path Delay Fault Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 31 (2) (2023)
Irith Pomeranz
Partially Specified Output Response for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Subashini Gopalsamy, Irith Pomeranz
Fully Deterministic Storage Based Logic Built-In Self-Test. VTS (2023)
Irith Pomeranz
Test Data Compression for Transparent-Scan Sequences. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Irith Pomeranz
Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests. IEEE Trans. Very Large Scale Integr. Syst. 31 (9) (2023)
Irith Pomeranz
Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs. VTS (2023)
Irith Pomeranz
Topping Off Test Sets Under Bounded Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Irith Pomeranz
Expanding a Pool of Functional Test Sequences to Support Test Compaction. VTS (2023)
Irith Pomeranz
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (4) (2023)
Irith Pomeranz
Sharing of Compressed Tests Among Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Irith Pomeranz
Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines. ITC (2023)
Irith Pomeranz
Storage and Counter Based Logic Built-In Self-Test. IEEE Access 11 (2023)
Irith Pomeranz
Storage-Based Logic Built-In Self-Test With Cyclic Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Irith Pomeranz
Diagnostic Test Point Insertion and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 31 (2) (2023)
Irith Pomeranz
Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models. ITC (2022)
Irith Pomeranz
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS (2022)
Irith Pomeranz
Storage-Based Logic Built-in Self-Test With Multicycle Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (10) (2022)
Irith Pomeranz
Test Sequences for Faults in the Scan Logic. IEEE Trans. Very Large Scale Integr. Syst. 30 (10) (2022)
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
Test Generation for an Iterative Design Flow with RTL Changes. ITC (2022)
Hari Addepalli, Irith Pomeranz
Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests. ACM Great Lakes Symposium on VLSI (2022)
Irith Pomeranz
Usable Circuits with Imperfect Scan Logic. ATS (2022)
Irith Pomeranz
Preponing Fault Detections for Test Compaction Under Transparent Scan. IEEE Trans. Very Large Scale Integr. Syst. 30 (10) (2022)
Irith Pomeranz
Static Test Compaction Using Independent Suffixes of a Transparent-Scan Sequence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
Fast Test Generation for Structurally Similar Circuits. VTS (2022)
Irith Pomeranz
Two-Dimensional Test Generation Objective. ATS (2022)
Irith Pomeranz
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Irith Pomeranz
Increasing the Fault Coverage of a Truncated Test Set. ACM Trans. Design Autom. Electr. Syst. 27 (6) (2022)
Irith Pomeranz
Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines. ATS (2022)
Irith Pomeranz
Storage-Based Logic Built-In Self-Test with Variable-Length Test Data. DFT (2022)
Irith Pomeranz
GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Irith Pomeranz
Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Irith Pomeranz
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Irith Pomeranz
Compaction of Compressed Bounded Transparent-Scan Test Sets. ACM Great Lakes Symposium on VLSI (2022)
Irith Pomeranz
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Irith Pomeranz
Covering Test Holes of Functional Broadside Tests. ACM Trans. Design Autom. Electr. Syst. 26 (3) (2021)
Irith Pomeranz, M. Enamul Amyeen
Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Irith Pomeranz
Zoom-In Feature for Storage-Based Logic Built-In Self-Test. DFT (2021)
Irith Pomeranz
Padding of LFSR Seeds for Reduced Input Test Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (5) (2021)
Irith Pomeranz
Maximal Independent Fault Set for Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (3) (2021)
Irith Pomeranz
Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests. ATS (2021)
Irith Pomeranz
PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
Irith Pomeranz, Xijiang Lin
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Irith Pomeranz
Compact Set of LFSR Seeds for Diagnostic Tests. VTS (2021)
Irith Pomeranz
Storage-Based Built-In Self-Test for Gate-Exhaustive Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (10) (2021)
Irith Pomeranz
Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors. ACM Trans. Design Autom. Electr. Syst. 26 (4) (2021)
Irith Pomeranz
Test Compaction by Backward and Forward Extension of Multicycle Tests. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
Irith Pomeranz
Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
Irith Pomeranz
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Irith Pomeranz, M. Enamul Amyeen
Logic Diagnosis with Hybrid Fail Data. ACM Trans. Design Autom. Electr. Syst. 26 (3) (2021)
Irith Pomeranz
Target Faults for Test Compaction Based on Multicycle Tests. ACM Trans. Design Autom. Electr. Syst. 25 (2) (2020)
Irith Pomeranz
Selection of Primary Output Vectors to Observe Under Multicycle Tests. IEEE Trans. Very Large Scale Integr. Syst. 28 (1) (2020)
Irith Pomeranz
Functional Broadside Tests Under Broadcast Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Irith Pomeranz, Srikanth Venkataraman
LFSR-Based Test Generation for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Irith Pomeranz
Non-Masking Non-Robust Tests for Path Delay Faults. VTS (2020)
Irith Pomeranz
Globally Functional Transparent-Scan Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Irith Pomeranz
LFSR-based generation of boundary-functional broadside tests. IET Comput. Digit. Tech. 14 (2) (2020)
Irith Pomeranz
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Irith Pomeranz
Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults. DFT (2020)
Irith Pomeranz, Sandip Kundu
Reduced Fault Coverage as a Target for Design Scaffolding Security. IOLTS (2020)
Irith Pomeranz
Reverse Low-Power Broadside Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (3) (2020)
Irith Pomeranz
Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Irith Pomeranz
Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests. IOLTS (2020)
Irith Pomeranz
Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Irith Pomeranz
Broad-Brush Compaction for Sequential Test Generation. IEEE Trans. Very Large Scale Integr. Syst. 28 (8) (2020)
Irith Pomeranz
Multicycle Broadside and Skewed-Load Tests for Test Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Irith Pomeranz
Broadside Tests for Transition and Stuck-At Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (8) (2020)
Irith Pomeranz
New Targets for Diagnostic Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Irith Pomeranz
RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation. IEEE Trans. Very Large Scale Integr. Syst. 28 (8) (2020)
Irith Pomeranz
Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs. VTS (2020)
Irith Pomeranz
Selecting Close-to-Functional Path Delay Faults for Test Generation. ITC (2020)
Irith Pomeranz
Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (12) (2019)
Irith Pomeranz
Updating the sets of target faults during test generation for multiple fault models. IET Comput. Digit. Tech. 13 (5) (2019)
Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS (2019)
Irith Pomeranz
Diagnostic Test Generation That Addresses Diagnostic Holes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (2) (2019)
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE (2019)
Irith Pomeranz
Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence. IEEE Trans. Very Large Scale Integr. Syst. 27 (6) (2019)
Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. VTS (2019)
Irith Pomeranz
Incomplete Tests for Undetectable Faults to Improve Test Set Quality. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Irith Pomeranz
Test Compaction by Test Removal Under Transparent Scan. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. 24 (4) (2019)
Irith Pomeranz
Test Compaction Under Bounded Transparent-Scan. VTS (2019)
Irith Pomeranz
Extended Transparent-Scan. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Irith Pomeranz
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation. ITC (2019)
Irith Pomeranz
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults. ITC (2019)

Irith Pomeranz.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Irith Pomeranz