Arani Sinha

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 19

Top Topics

Data Corruption

Distributed Digital Library

Top Venues

Publications

Arani Sinha, Adit D. Singh
Innovative Practices Track: Session 2 Silent Data Corruption. VTS (2024)
Arani Sinha, Stefano Di Carlo
Innovative Practices Track: Session 4 AI Applications in Test. VTS (2024)
Arani Sinha
Innovative Practices Track: Session 3 Test and Functional Safety Standards. VTS (2024)
Arani Sinha, Glenn Colón-Bonet, Michael Fahy, Pankaj Pant, Haijing Mao, Akhilesh Shukla
Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure. ITC (2023)
Arani Sinha, Yonsang Cho, Jon Easter, Meizel V. Leiva Rojas
Multi-die Parallel Test Fabric for Scalability and Pattern Reusability. ITC (2022)
Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS (2022)
Arani Sinha
Innovative Practices Track: Silent Data Errors. VTS (2022)
Arani Sinha
Innovative Practices Track: Next Generation Test Standards. VTS (2022)
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. VTS (2021)
Sandip Ray, Arani Sinha
Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction. ETS (2021)
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. ITC (2020)
Ankit Shah, Raman Nayyar, Arani Sinha
Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests. IEEE Des. Test 37 (4) (2020)
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE (2019)
Sujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology. ITC (2019)
Ankit Shah, Raman Nayyar, Arani Sinha
Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests. VTS (2019)
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. 24 (4) (2019)
Salem Abdennadher, Arani Sinha, Yonghyun Kim
Analog/Mixed Signal IP DFx from a Foundry perspective. LATS (2019)
Arani Sinha, Nitin Chaudhary
Innovative practices session 1C screening for layout sensitive defects. VTS (2017)
Arani Sinha, Sujay Pandey, Ayush Singhal, Alodeep Sanyal, Alan Schmaltz
DFM-aware fault model and ATPG for intra-cell and inter-cell defects. ITC (2017)
Bo Yao, Arani Sinha, Irith Pomeranz
Path selection based on static timing analysis considering input necessary assignments. VTS (2013)
Suriyaprakash Natarajan, Arani Sinha
The buck stops with wafer test: Dream or reality? VTS (2011)
Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou
A Novel mechanism for speed characterization during delay test. VTS (2011)
Arani Sinha, Suriyaprakash Natarajan
The bang for the buck with resiliency: Yield or field? VTS (2011)
Arani Sinha
Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality? VTS (2010)
Arani Sinha, Amitava Majumdar, Vasu Ganti
Panel: Analog Characterization and Test: The Long Road to Realization. VTS (2009)
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. ATS (2008)
Santosh Shah, Arani Sinha, Li Song, Narain D. Arora
On-Chip Inductance in X Architecture Enabled Design. ISQED (2007)
Arani Sinha, Shahin Nazarian, T. M. Mak
Simulating the Effects of Process Variations on Capacitive Crosstalk. ICECS (2006)
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium (2003)
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD (1999)
Arani Sinha, Salim Chowdhury
Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction. CICC (1999)
Subhas C. Nandy, Arani Sinha, Bhargab B. Bhattacharya
Location of the Largest Empty Rectangle among Arbitrary Obstacles. FSTTCS (1994)