Suriyaprakash Natarajan

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 25

Top Topics

Analog Circuits

Production Cost

Compression Scheme

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Ayush Arunachalam, Ian Kintz, Suvadeep Banerjee, Arnab Raha, Xiankun Jin, Fei Su, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Suriyaprakash Natarajan, Kanad Basu
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. CoRR (2024)
Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (1) (2024)
Suhas Krishna Kashyap, Chinmaye Raghavendra, Suriyaprakash Natarajan, Sule Ozev
Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors. VTS (2024)
Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators. IEEE Des. Test 40 (2) (2023)
Ayush Arunachalam, Sanjay Das, Monikka Rajan, Fei Su, Xiankun Jin, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu
Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits. ITC (2023)
Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Fei Su, Suriyaprakash Natarajan, Kanad Basu
Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators. IEEE Trans. Computers 72 (8) (2023)
Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (4) (2023)
Shiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris
A defect tolerance framework for improving yield. DAC (2022)
Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS (2022)
Suriyaprakash Natarajan, Abhijit Sathaye, Chaitali Oak, Nipun Chaplot, Suvadeep Banerjee
DEFCON: Defect Acceleration through Content Optimization. ITC (2022)
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. VTS (2021)
Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators. ISQED (2021)
Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29 (3) (2021)
Srikanth Venkat Raman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. ITC (2020)
Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen
Automated Design For Yield Through Defect Tolerance. VTS (2020)
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. ITC (2020)
Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
A novel test compression algorithm for analog circuits to decrease production costs. Integr. 58 (2017)
Suriyaprakash Natarajan, Li-C. Wang
Session 4B - Panel data analytics in semiconductor manufacturing. VTS (2016)
Suvadeep Banerjee, Suriyaprakash Natarajan
Infant mortality tests for analog and mixed-signal circuits. VTS (2016)
Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, Arijit Raychowdhury
Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary
Fault simulation for analog test coverage. ITC (2016)
Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
Every test makes a difference: Compressing analog tests to decrease production costs. ASP-DAC (2016)
Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan
Fast eye diagram analysis for high-speed CMOS circuits. DATE (2015)
Chong Li, Suriyaprakash Natarajan, C.-J. Richard Shi
Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. ICECS (2015)
Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury
A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. ATS (2015)
Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation. ITC (2014)
Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas
Special session 12B: Panel post-silicon validation & test in huge variance era. VTS (2013)
Debesh Bhatta, Ishita Mukhopadhyay, Suriyaprakash Natarajan, Prashant Goteti, Bin Xue
Framework for analog test coverage. ISQED (2013)
Mustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, Prashant Goteti
Scalable and efficient analog parametric fault identification. ICCAD (2013)
Suriyaprakash Natarajan, Arani Sinha
The buck stops with wafer test: Dream or reality? VTS (2011)
Arani Sinha, Suriyaprakash Natarajan
The bang for the buck with resiliency: Yield or field? VTS (2011)
Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche
Path coverage based functional test generation for processor marginality validation. ITC (2010)
Suriyaprakash Natarajan
Innovative practices session 9C: Implications of power delivery network for validation and testing. VTS (2010)
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan
On efficient generation of instruction sequences to test for delay defects in a processor. ACM Great Lakes Symposium on VLSI (2008)
I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta
On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC (2008)
Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani
Case Study on Speed Failure Causes in a Microprocessor. IEEE Des. Test Comput. 25 (3) (2008)
Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil
The Region-Exhaustive Fault Model. ATS (2007)
Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
Selecting High-Quality Delay Tests for Manufacturing Test and Debug. DFT (2006)
Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty
Path Delay Fault Simulation on Large Industrial Designs. VTS (2006)
Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. Asian Test Symposium (2005)
Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
XIDEN: Crosstalk Target Identification Framework. ITC (2002)
Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
Switch-level delay test of domino logic circuits. ITC (2001)
Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
Switch-level delay test. ITC (1999)
Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta
Process Variations and their Impact on Circuit Operation. DFT (1998)