A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators.
Ayush ArunachalamShamik KunduArnab RahaSuvadeep BanerjeeSuriyaprakash NatarajanKanad BasuPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2023)
Keyphrases
- deep learning
- compression scheme
- low power
- systolic array
- single chip
- low cost
- power consumption
- high speed
- image compression
- data flow
- unsupervised learning
- data compression
- compression ratio
- parallel architecture
- entropy coding
- compression algorithm
- mental models
- real time
- parallel processing
- wavelet transform
- image sensor
- machine learning
- multiresolution
- cmos technology
- supervised learning
- hardware implementation
- image data
- pattern recognition
- feature extraction