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On efficient generation of instruction sequences to test for delay defects in a processor.
Sankar Gurumurthy
Ramtilak Vemu
Jacob A. Abraham
Suriyaprakash Natarajan
Published in:
ACM Great Lakes Symposium on VLSI (2008)
Keyphrases
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test sequences
multimedia
instruction set
parallel processing
parallel architectures
level parallelism
hidden markov models
computationally efficient
test cases
generation process