Pascal Andreas Meinerzhagen

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 6

Top Topics

Automated Design

Scalable Distributed

Gate Dielectrics

Top Venues

IEEE J. Solid State Circuits

Publications

Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen
Automated Design For Yield Through Defect Tolerance. VTS (2020)
Suyoung Bang, Minki Cho, Pascal Andreas Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. IEEE J. Solid State Circuits 55 (7) (2020)
Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC (2019)
Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54 (1) (2019)
Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS (2017)
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Adam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. ASP-DAC (2015)
Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. ISCAS (2015)
Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE (2015)
Oskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. ESSCIRC (2014)
Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS (2014)
Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs (4) (2014)
Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici
FireBird: PowerPC e200 based SoC for high temperature operation. CICC (2013)
Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. ESSCIRC (2012)
Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. VLSI-SoC (Selected Papers) (2012)
Rashid Iqbal, Pascal Andreas Meinerzhagen, Andreas Peter Burg
Two-port low-power gain-cell storage array: Voltage scaling and retention time. ISCAS (2012)
Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. VLSI-SoC (2012)
Pascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. ACM Great Lakes Symposium on VLSI (2011)
Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues
Domain in 65-nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (2) (2011)
Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues
Synthesis strategies for sub-VT systems. ECCTD (2011)