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A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.
Pascal Andreas Meinerzhagen
Oskar Andersson
Babak Mohammadi
S. M. Yasser Sherazi
Andreas Peter Burg
Joachim Neves Rodrigues
Published in:
ESSCIRC (2012)
Keyphrases
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random access memory
analog to digital converter
knowledge base
random access
low voltage
low cost
high speed
data access
design considerations
memory access
nm technology
real time
memory usage
memory space
hash table