S. M. Yasser Sherazi

Publication Activity (10 Years)

Years Active: 2010-2015
Publications (10 Years): 0

Top Topics

Metal Oxide Semiconductor

Vlsi Architecture

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland, Viktor Öwall
Low Power Analog and Digital (7, 5) Convolutional Decoders in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Peter Nilsson, Mohammed Azher Ali, Manivannan Ethiraj, S. M. Yasser Sherazi
Supply-voltage down conversion for digital CMOS designs. ICECS (2014)
S. M. Yasser Sherazi, Henrik Sjöland, Peter Nilsson
A digital baseband for low power FSK based receiver in 65 nm CMOS. ICECS (2014)
Henrik Sjöland, John B. Anderson, Carl Bryant, Rohit Chandra, Ove Edfors, Anders J. Johansson, Nafiseh Seyed Mazloum, Reza Meraji, Peter Nilsson, Dejan Radjen, Joachim Neves Rodrigues, S. M. Yasser Sherazi, Viktor Öwall
Ultra low power transceivers for wireless sensors and body area networks. ISMICT (2014)
Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland, Viktor Öwall
Analog and digital approaches for an energy efficient low complexity channel decoder. ISCAS (2013)
Peter Nilsson, Anusha Gundarapu, S. M. Yasser Sherazi
Power savings in digital filters for wireless communication. ECCTD (2013)
S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjöland, Peter Nilsson
domain. Microprocess. Microsystems 37 (4-5) (2013)
Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. ESSCIRC (2012)
S. M. Yasser Sherazi, Peter Nilsson, Henrik Sjöland, Joachim Neves Rodrigues
A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. ICECS (2012)
Henrik Sjöland, John B. Anderson, Carl Bryant, Rohit Chandra, Ove Edfors, Anders J. Johansson, Nafiseh Seyed Mazloum, Reza Meraji, Peter Nilsson, Dejan Radjen, Joachim Neves Rodrigues, S. M. Yasser Sherazi, Viktor Öwall
A Receiver Architecture for Devices in Wireless Body Area Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (1) (2012)
Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues
Domain in 65-nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (2) (2011)
Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. NORCHIP (2011)
Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues
Synthesis strategies for sub-VT systems. ECCTD (2011)
S. M. Yasser Sherazi, Peter Nilsson, Omer Can Akgun, Henrik Sjöland, Joachim Neves Rodrigues
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. ISCAS (2011)
S. M. Yasser Sherazi, Shahzad Asif, Erik Backenius, Mark Vesterbacka
Reduction of Substrate Noise in Sub Clock Frequency Range. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2010)