Mark Vesterbacka

Publication Activity (10 Years)

Years Active: 1994-2018
Publications (10 Years): 11

Top Topics

Data Conversion

Sampling Strategies

Phase Locked Loop

Reduced Complexity

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Mark Vesterbacka, Vishnu Unnikrishnan
Ring Counters as Phase Accumulator in VCO-Based ADCs. ICECS (2018)
Shahzad Asif, Mark Vesterbacka
An RNS based modular multiplier with reduced complexity. NORCAS (2017)
Vishnu Unnikrishnan, Mark Vesterbacka
Mitigation of Sampling Errors in VCO-Based ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Vishnu Unnikrishnan, Mark Vesterbacka
Mixed-Signal Design Using Digital CAD. ISVLSI (2016)
Vishnu Unnikrishnan, Mark Vesterbacka
Linearization of VCO-based ADCs using asynchronous sigma-delta modulation. MWSCAS (2016)
Vishnu Unnikrishnan, Mark Vesterbacka, Atila Alvandpour
VCO-based ADCs for IoT applications. ISIC (2016)
Vishnu Unnikrishnan, Mark Vesterbacka
Design of a VCO-based ADC in 28 nm CMOS. NORCAS (2016)
Vishnu Unnikrishnan, Srinivasa Rao Pathapati, Mark Vesterbacka
A fully synthesized all-digital VCO-based analog-to-digital converter. NORCAS (2015)
Vishnu Unnikrishnan, Mark Vesterbacka
Linearization of synthesizable VCO-based ADCs using delta modulation. ECCTD (2015)
Vishnu Unnikrishnan, Mark Vesterbacka
A NAND gate based standard cell VCO for use in synthesizable ADCs. NORCAS (2015)
Muhammad Touqir Pasha, Niklas U. Andersson, Mark Vesterbacka
Power-efficient time-to-digital converter for all-digital frequency locked loops. ECCTD (2015)
Vishnu Unnikrishnan, Mark Vesterbacka
Time-Mode Analog-to-Digital Conversion Using Standard Cells. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Niklas U. Andersson, Mark Vesterbacka
A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture. IEEE Trans. Circuits Syst. II Express Briefs (10) (2014)
Muhammad Touqir Pasha, Mark Vesterbacka
A modified switching scheme for multiplexer based thermometer-to-binary encoders. NORCHIP (2014)
Shahzad Asif, Mark Vesterbacka
Performance analysis of radix-4 adders. Integr. 45 (2) (2012)
Muhammad Touqir Pasha, Mark Vesterbacka
Frequency control schemes for single-ended ring oscillators. ECCTD (2011)
Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner, Kent Palmkvist, Mark Vesterbacka
Calibration of high-resolution flash ADCS based on histogram test methods. ICECS (2010)
S. M. Yasser Sherazi, Shahzad Asif, Erik Backenius, Mark Vesterbacka
Reduction of Substrate Noise in Sub Clock Frequency Range. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2010)
Erik Backenius, Mark Vesterbacka, V. B. Settu
Reduction of simultaneous switching noise in analog signal band. ECCTD (2007)
Erik Sall, Mark Vesterbacka
Thermometer-to-binary decoders for flash analog-to-digital converters. ECCTD (2007)
Erik Backenius, Mark Vesterbacka
Effect of Simultaneous Switching Noise on an Analog Filter. ICECS (2006)
Magnus Karlsson, Mark Vesterbacka
Digit-serial/parallel multipliers with improved throughput and latency. ISCAS (2006)
K. Ola Andersson, Mark Vesterbacka
A yield-enhancement strategy for binary-weighted DACs. ECCTD (2005)
Krister Landernäs, Johnny Holmberg, Mark Vesterbacka
Glitch reduction in digit-serial recursive filters using retiming. ICECS (2005)
Erik Sall, Mark Vesterbacka
6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications. ECCTD (2005)
K. Ola Andersson, Mark Vesterbacka
Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2005)
Erik Sall, Mark Vesterbacka
Design of a Comparator in CMOS SOI. IWSOC (2004)
K. Ola Andersson, Mark Vesterbacka
A Parameterized Cell-Based Design Approach for Digital-to-Analog Converters. IWSOC (2004)
Krister Landernäs, Johnny Holmberg, Mark Vesterbacka
A high-speed low-latency digit-serial hybrid adder. ISCAS (3) (2004)
Erik Sall, Mark Vesterbacka, K. Ola Andersson
A study of digital decoders in flash analog-to-digital converters. ISCAS (1) (2004)
Magnus Karlsson, Mark Vesterbacka, Wlodek Kulesza
A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers. ISCAS (2) (2004)
K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, J. Jacob Wikner
A differential DAC architecture with variable common-mode level. ISCAS (1) (2002)
Robert Hägglund, Per Löwenborg, Mark Vesterbacka
A polynomial-based division algorithm. ISCAS (3) (2002)
Mark Vesterbacka, J. Jacob Wikner
Design of encoders for linear-coded D/A converters. ISCAS (1) (2001)
Mark Vesterbacka
A static CMOS master-slave flip-flop experiment. ICECS (2000)
Mikael Karlsson Rudberg, Mark Vesterbacka, Niklas U. Andersson, J. Jacob Wikner
Glitch minimization and dynamic element matching in D/A converters. ICECS (2000)
Mark Vesterbacka, Mikael Rudberg, J. Jacob Wikner, Niklas U. Andersson
Dynamic element matching in D/A converters with restricted scrambling. ICECS (2000)
Mark Vesterbacka
A robust differential scan flip-flop. ISCAS (1) (1999)
Kent Palmkvist, Mark Vesterbacka, Lars Wanhammar
Implementation of static DSP algorithms using multiplexed PE: s. ICECS (1996)
Mark Vesterbacka, Kent Palmkvist, Lars Wanhammar
Sign-extension and quantization in bit-serial digital filters. ICECS (1996)
Mark Vesterbacka, Kent Palmkvist, Peter Sandberg, Lars Wanhammar
Implementation of Fast Bit-Serial Lattice Wave Digital Filters. ISCAS (1994)
Peter Nilsson, Mats Torkelson, Kent Palmkvist, Mark Vesterbacka, Lars Wanhammar
A Bit-Serial CMOS Digital IF-Filter for Mobile Radio Using an On-Chip Clock. Mobile Communications (1994)