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A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture.
Niklas U. Andersson
Mark Vesterbacka
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2014)
Keyphrases
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data conversion
management system
power consumption
phase locked loop
low power
digital media
mixed signal
low voltage
real time
neural network
master slave
network architecture
control method
software architecture
high voltage
sigma delta
analog to digital converter