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Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain.
S. M. Yasser Sherazi
Peter Nilsson
Omer Can Akgun
Henrik Sjöland
Joachim Neves Rodrigues
Published in:
ISCAS (2011)
Keyphrases
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circuit design
case study
user interface
high speed
cmos technology
metal oxide semiconductor
image processing
multiscale
design process
filter design