Robert Giterman

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 30

Top Topics

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Roman Golman, Netanel Nachum, Tomer Cohen, Robert Giterman, Adam Teman
Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros. IEEE Access 9 (2021)
Yoav Weizman, Robert Giterman, Oron Chertkow, Maoz Wicentowski, Itamar Levi, Ilan Sever, Ishai Kehati, Osnat Keren, Alexander Fish
Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads. IEEE Access 9 (2021)
Odem Harel, Yarden Nachum, Robert Giterman
Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM. Microelectron. J. 101 (2020)
Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg
Lupulus: A Flexible Hardware Accelerator for Neural Networks. ICASSP (2020)
Roman Golman, Robert Giterman, Odem Harel, Adam Teman
Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique. ISCAS (2020)
Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg
Lupulus: A Flexible Hardware Accelerator for Neural Networks. CoRR (2020)
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. ISCAS (2020)
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
Gain-Cell Embedded DRAMs: Modeling and Design Space. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
Gain-Cell Embedded DRAMs: Modeling and Design Space. ISCAS (2020)
Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (4) (2020)
Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. A-SSCC (2019)
Robert Giterman, Maoz Wicentowski, Oron Chertkow, Ilan Sever, Ishai Kehati, Yoav Weizman, Osnat Keren, Alexander Fish
Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. ESSCIRC (2019)
Robert Giterman, Osnat Keren, Alexander Fish
A 7T Security Oriented SRAM Bitcell. IEEE Trans. Circuits Syst. II Express Briefs (8) (2019)
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Robert Giterman, Roman Golman, Adam Teman
Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection. IEEE Access 7 (2019)
Robert Giterman, Roman Golman, Amir Shalom, Or Maltabashi, Alexander Fish, Adam Teman
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. ISCAS (2018)
Or Maltabashi, Hanan Marinberg, Robert Giterman, Adam Teman
A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. ISCAS (2018)
Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications. IEEE J. Solid State Circuits 53 (7) (2018)
Robert Giterman, Yoav Weizman, Adam Teman
Gain-Cell Embedded DRAM-Based Physical Unclonable Function. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Robert Giterman, Alexander Fish, Andreas Burg, Adam Teman
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2018)
Amir Shalom, Robert Giterman, Adam Teman
High Density GC-eDRAM Design in 16nm FinFET. ICECS (2018)
Roman Golman, Robert Giterman, Adam Teman
Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. ICECS (2018)
Robert Giterman, Maoz Vicentowski, Itamar Levi, Yoav Weizman, Osnat Keren, Alexander Fish
Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Natan Vinshtok-Melnik, Robert Giterman, Joseph Shor
Ultra miniature offset cancelled bandgap reference with ±0.534% inaccuracy from -10°C to 110°C. ISCAS (2017)
Robert Giterman, Lior Atias, Adam Teman
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Robert Giterman, Adam Teman, Pascal Meinerzhagen
Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)
Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. ESSCIRC (2017)
Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS (2016)
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Shrikanth Ganapathy, Adam Teman, Robert Giterman, Andreas Burg, Georgios Karakonstantis
Approximate computing with unreliable dynamic memories. NEWCAS (2015)
Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE (2015)
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS (2014)
Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs (4) (2014)