Adam Teman

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 62

Top Topics

Failure Detection

Approximate Matching

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Roman Golman, Avinoam Segev, Adam Teman
A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications. PRIME (2024)
Yehuda Kra, Yehuda Rudin, Alexander Fish, Adam Teman
Basecalling by Statistical Profiling and Hardware-Accelerated Convolutional Neural Network. PRIME (2024)
Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits
FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access 12 (2024)
Yehuda Kra, Naama Kra, Adam Teman
Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors. DATE (2024)
Inbal Stanger, Noam Roknian, Netanel Shavit, Yonatan Shoshan, Yoav Weizman, Adam Teman, Edoardo Charbon, Alexander Fish
Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (3) (2024)
Yehuda Kra, Yonatan Shoshan, Yehuda Rudin, Adam Teman
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
Noam Roknian, Yonatan Shoshan, Inbal Stanger, Menachem Goldzweig, Yoav Weizmann, Adam Teman, Edoardo Charbon, Alexander Fish
Methodologies for Device Characterization in Cryogenic Temperatures. PRIME (2024)
Hanan Marinberg, Esteban Garzón, Tzachi Noy, Marco Lanuzza, Adam Teman
Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access 11 (2023)
Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS (2023)
Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access 11 (2023)
Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Noam Roknian, Yonatan Shoshan, Inbal Stanger, Adam Teman, Edoardo Charbon, Alexander Fish
Overview of Cryogenic Operation in Nanoscale Technology Nodes. LASCAS (2023)
Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access 10 (2022)
Inbal Stanger, Noam Roknian, Yonatan Shoshan, Zafrir Levy, Yoav Weizman, Edoardo Charbon, Adam Teman, Alexander Fish
Evaluation of Dual Mode Logic Under Cryogenic Temperatures. ISCAS (2022)
Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits
AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro 42 (6) (2022)
Yehuda Kra, Yoav Weitzman, Adam Teman
SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. DCIS (2022)
Yehuda Kra, Adam Teman
Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing. ISCAS (2022)
Esteban Garzón, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weizman, Marco Lanuzza, Adam Teman
A RISC-V-based Research Platform for Rapid Design Cycle. ISCAS (2022)
Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits
EDAM: edit distance tolerant approximate matching content addressable memory. ISCA (2022)
Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR (2022)
Roman Golman, Netanel Nachum, Tomer Cohen, Robert Giterman, Adam Teman
Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros. IEEE Access 9 (2021)
Esteban Garzón, Yosi Greenblatt, Odem Harel, Marco Lanuzza, Adam Teman
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Yehuda Kra, Tzachi Noy, Adam Teman
WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining. DATE (2021)
Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR (2021)
Einat Levy, Aharon Sfez, Roman Golman, Odem Harel, Adam Teman
4T Gain-Cell Providing Unlimited Availability through Hidden Refresh with 1W1R Functionality. ISCAS (2021)
Or Maltabashi, Yehuda Kra, Adam Teman
Physically Aware Affinity-Driven Multiplier Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Yehuda Kra, Tzachi Noy, Adam Teman
WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation. DATE (2020)
Roman Golman, Robert Giterman, Odem Harel, Adam Teman
Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique. ISCAS (2020)
Tzachi Noy, Adam Teman
Design of a Refresh-Controller for GC-eDRAM Based FIFOs. IEEE Trans. Circuits Syst. (12) (2020)
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. ISCAS (2020)
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
Gain-Cell Embedded DRAMs: Modeling and Design Space. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
Gain-Cell Embedded DRAMs: Modeling and Design Space. ISCAS (2020)
Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (4) (2020)
Tom Munk, Hillel Kugler, Ofir Maori, Adam Teman
TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches. VLSI-DAT (2019)
Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Robert Giterman, Roman Golman, Adam Teman
Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection. IEEE Access 7 (2019)
Robert Giterman, Roman Golman, Amir Shalom, Or Maltabashi, Alexander Fish, Adam Teman
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. ISCAS (2018)
Or Maltabashi, Hanan Marinberg, Robert Giterman, Adam Teman
A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. ISCAS (2018)
Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications. IEEE J. Solid State Circuits 53 (7) (2018)
Robert Giterman, Yoav Weizman, Adam Teman
Gain-Cell Embedded DRAM-Based Physical Unclonable Function. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Robert Giterman, Alexander Fish, Andreas Burg, Adam Teman
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2018)
Amir Shalom, Robert Giterman, Adam Teman
High Density GC-eDRAM Design in 16nm FinFET. ICECS (2018)
Roman Golman, Robert Giterman, Adam Teman
Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. ICECS (2018)
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37 (5) (2017)
Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. ACM Trans. Design Autom. Electr. Syst. 22 (4) (2017)
Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Robert Giterman, Lior Atias, Adam Teman
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Robert Giterman, Adam Teman, Pascal Meinerzhagen
Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)
Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. ESSCIRC (2017)
Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing. CoRR (2017)
Amit Kazimirsky, Adam Teman, Noa Edri, Alexander Fish
A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications. IEEE Trans. Very Large Scale Integr. Syst. 25 (9) (2017)
Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS (2016)
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Lior Moyal, Itamar Levi, Adam Teman, Alexander Fish
Synthesis of Dual Mode Logic. Integr. 55 (2016)
Reza Ghanaatian, Paul N. Whatmough, Jeremy Constantin, Adam Teman, Andreas Burg
A low-power correlator for wakeup receivers with algorithm pruning through early termination. ISCAS (2016)
Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. ESSCIRC (2016)
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips (2016)
Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2016)
Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. ACM Trans. Design Autom. Electr. Syst. 21 (4) (2016)
Adam Teman, Roman Visotsky
A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Adam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. ASP-DAC (2015)
Andrea Bonetti, Adam Teman, Andreas Burg
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. ISCAS (2015)
Shrikanth Ganapathy, Adam Teman, Robert Giterman, Andreas Burg, Georgios Karakonstantis
Approximate computing with unreliable dynamic memories. NEWCAS (2015)
Shrikanth Ganapathy, Georgios Karakonstantis, Adam Teman, Andreas Burg
Mitigating the impact of faults in unreliable memories for error-resilient applications. DAC (2015)
Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE (2015)
Hadar Dagan, Aviv Shapira, Adam Teman, Anatoli Mordakhay, Samuel Jameson, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin, Eran Socher, Alexander Fish
A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory. IEEE J. Solid State Circuits 49 (9) (2014)
Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS (2014)
Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs (4) (2014)
Adam Teman, Anatoli Mordakhay, Alexander Fish
Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell. Microelectron. J. 44 (3) (2013)
Hadar Dagan, Adam Teman, Evgeny Pikhay, Vladislav Dayan, Anatoli Mordakhay, Yakov Roizin, Alexander Fish
A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory. IEEE J. Solid State Circuits 48 (6) (2013)
Janna Mezhibovsky, Adam Teman, Alexander Fish
State space modeling for sub-threshold SRAM stability analysis. ISCAS (2012)
Adam Teman, Anatoli Mordakhay, Janna Mezhibovsky, Alexander Fish
A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Arthur Spivak, Adam Teman, Alexander Belenky, Orly Yadid-Pecht, Alexander Fish
Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel. Sensors 12 (8) (2012)
Hadar Dagan, Adam Teman, Alexander Fish, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
A low-cost low-power non-volatile memory for RFID applications. ISCAS (2012)
Hadar Dagan, Adam Teman, Alexander Fish, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
A GIDL free tunneling gate driver for a low power non-volatile memory array. ISCAS (2012)
Janna Mezhibovsky, Adam Teman, Alexander Fish
Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM. SoCC (2011)
Adam Teman, Lidor Pergament, Omer Cohen, Alexander Fish
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM). IEEE J. Solid State Circuits 46 (11) (2011)
Sagi Fisher, Adam Teman, Dmitry Vaysman, Alexander Gertsman, Orly Yadid-Pecht, Alexander Fish
Ultra-low Power Subthreshold Flip-flop Design. ISCAS (2009)
Adam Teman, Sagi Fisher, Liby Sudakov, Alexander Fish, Orly Yadid-Pecht
Autonomous CMOS image sensor for real time target detection and tracking. ISCAS (2008)