Leonid Yavits

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 51

Top Topics

Energy Efficiency

Hamming Distance

Sequence Alignment

Top Venues

IEEE Comput. Archit. Lett.

Publications

Zuher Jahshan, Leonid Yavits
ViTAL: Vision TrAnsformer based Low coverage SARS-CoV-2 lineage assignment. Bioinform. 40 (3) (2024)
Zuher Jahshan, Esteban Garzón, Leonid Yavits
ViRAL: Vision Transformer Based Accelerator for ReAL Time Lineage Assignment of Viral Pathogens. IEEE Access 12 (2024)
Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits
FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access 12 (2024)
Zuher Jahshan, Leonid Yavits
MajorK: Majority Based kmer Matching in Commodity DRAM. IEEE Comput. Archit. Lett. 23 (1) (2024)
Leonid Yavits
DRAMA: Commodity DRAM Based Content Addressable Memory. IEEE Comput. Archit. Lett. 23 (1) (2024)
Netanel Shavit, Inbal Stanger, Ramiro Taco, Leonid Yavits, Alexander Fish
Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications. PRIME (2024)
Zuher Jahshan, Itay Merlin, Esteban Garzón, Leonid Yavits
DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification. MICRO (2023)
Leonid Yavits
DRAMA: Commodity DRAM based Content Addressable Memory. CoRR (2023)
Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS (2023)
Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access 11 (2023)
Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. IEEE Trans. Very Large Scale Integr. Syst. 31 (9) (2023)
Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory. CoRR (2023)
Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access 10 (2022)
Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits
AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro 42 (6) (2022)
Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
FiltPIM: In-Memory Filter for DNA Sequencing. CoRR (2022)
Leonid Yavits, Roman Kaplan, Ran Ginosar
GIRAF: General Purpose In-Storage Resistive Associative Framework. IEEE Trans. Parallel Distributed Syst. 33 (2) (2022)
Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits
EDAM: edit distance tolerant approximate matching content addressable memory. ISCA (2022)
Zuher Jahshan, Leonid Yavits
CoViT: Real-time phylogenetics for the SARS-CoV-2 pandemic using Vision Transformers. CoRR (2022)
Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR (2021)
Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
FiltPIM: In-Memory Filter for DNA Sequencing. ICECS (2021)
Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish
Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS (2020)
Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. ICCD (2020)
Roman Kaplan, Leonid Yavits, Ran Ginosar
BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. SYSTOR (2020)
Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS (2020)
Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish
Dual Mode Logic Address Decoder. ISCAS (2020)
Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. CoRR (2020)
Leonid Yavits, Roman Kaplan, Ran Ginosar
AIDA: Associative DNN Inference Accelerator. CoRR (2019)
Leonid Yavits, Roman Kaplan, Ran Ginosar
POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. PACT (2019)
Roman Kaplan, Leonid Yavits, Ran Ginosar
POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. PACT (2019)
Roman Kaplan, Leonid Yavits, Ran Ginosar
RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping. IEEE Micro 39 (4) (2019)
Roman Kaplan, Leonid Yavits, Ran Ginosar
BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. CoRR (2019)
Roman Kaplan, Leonid Yavits, Ran Ginosar
RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping. CoRR (2018)
Leonid Yavits, Roman Kaplan, Ran Ginosar
PRINS: Resistive CAM Processing in Storage. CoRR (2018)
Leonid Yavits, Roman Kaplan, Ran Ginosar
Enabling Full Associativity with Memristive Address Decoder. IEEE Micro 38 (5) (2018)
Leonid Yavits, Ran Ginosar
Accelerator for Sparse Machine Learning. IEEE Comput. Archit. Lett. 17 (1) (2018)
Leonid Yavits, Amir Morad, Ran Ginosar
Cache Hierarchy Optimization. CoRR (2017)
Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR (2017)
Leonid Yavits, Uri C. Weiser, Ran Ginosar
Resistive Address Decoder. IEEE Comput. Archit. Lett. 16 (2) (2017)
Leonid Yavits, Amir Morad, Ran Ginosar
Sparse Matrix Multiplication On An Associative Processor. CoRR (2017)
Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro 37 (4) (2017)
Roman Kaplan, Leonid Yavits, Ran Ginosar
From Processing-in-Memory to Processing-in-Storage. Supercomput. Front. Innov. 4 (3) (2017)
Leonid Yavits, Amir Morad, Ran Ginosar
The Effect of Temperature on Amdahl Law in 3D Multicore Era. CoRR (2017)
Leonid Yavits, Ran Ginosar
Sparse Matrix Multiplication on CAM Based Accelerator. CoRR (2017)
Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar
MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR (2017)
Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar
Deduplication in resistive content addressable memory based solid state drive. PATMOS (2016)
Leonid Yavits, Amir Morad, Ran Ginosar
Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. CoRR (2016)
Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser
Convex Optimization of Real Time SoC. CoRR (2016)
Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar
Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. 12 (4) (2016)
Leonid Yavits, Amir Morad, Ran Ginosar
The Effect of Temperature on Amdahl Law in 3D Multicore Era. IEEE Trans. Computers 65 (6) (2016)
Leonid Yavits, Amir Morad, Ran Ginosar
Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. IEEE Trans. Computers 64 (2) (2015)
Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar
Resistive Associative Processor. IEEE Comput. Archit. Lett. 14 (2) (2015)
Leonid Yavits, Amir Morad, Ran Ginosar
Sparse Matrix Multiplication On An Associative Processor. IEEE Trans. Parallel Distributed Syst. 26 (11) (2015)
Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser
Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. 13 (1) (2014)
Leonid Yavits, Amir Morad, Ran Ginosar
Cache Hierarchy Optimization. IEEE Comput. Archit. Lett. 13 (2) (2014)
Amir Morad, Leonid Yavits, Ran Ginosar
Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. PATMOS (2014)
Amir Morad, Leonid Yavits, Ran Ginosar
Convex optimization of resource allocation in asymmetric and heterogeneous SoC. PATMOS (2014)
Amir Morad, Leonid Yavits, Ran Ginosar
GP-SIMD Processing-in-Memory. ACM Trans. Archit. Code Optim. 11 (4) (2014)
Leonid Yavits, Amir Morad, Ran Ginosar
The effect of communication and synchronization on Amdahl's law in multicore systems. Parallel Comput. 40 (1) (2014)
Leonid Yavits, Amir Morad, Ran Ginosar
3D cache hierarchy optimization. 3DIC (2013)
Leonid Yavits, Amir Morad, Ran Ginosar
3D Cache Hierarchy Optimization. CoRR (2013)
Leonid Yavits, Amir Morad, Ran Ginosar
Thermal analysis of 3D associative processor. CoRR (2013)
Leonid Yavits, Amir Morad, Ran Ginosar
The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems. CoRR (2013)